SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 176

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

• UNALIGN_TRP
Enables unaligned access traps:
0: do not trap unaligned halfword and word accesses
1: trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND
Enables unprivileged software access to the STIR, see
0: disable
1: enable.
• NONEBASETHRDENA
Indicates how the processor enters Thread mode:
0: processor can enter Thread mode only when no exception is active.
1: processor can enter Thread mode from any level under the control of an EXC_RETURN value, see
page
11.21.9
176
176
82.
SAM3X/A
SAM3X/A
System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have
configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in
their attributes.
The system fault handlers and the priority field and register for each handler are:
Table 11-32. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and
bits[3:0] read as zero and ignore writes.
Handler
Memory management
fault
Bus fault
Usage fault
SVCall
PendSV
SysTick
Field
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
“Software Trigger Interrupt Register” on page
“System Handler Priority Register 1” on page 177
“System Handler Priority Register 2” on page 178
“System Handler Priority Register 3” on page 178
Register description
Table 11-30 on page 165
162:
“Exception return” on
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
for