SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 598

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

30.7.1.1
598
598
SAM3X/A
SAM3X/A
Clock Divider
The receiver clock can be generated by:
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the
receiver block can generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
Figure 30-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division
by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this
field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Mas-
ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is even or odd.
Figure 30-5.
• an external clock received on the RK I/O pad
• the transmitter clock
• the internal clock divider
Divided Clock Generation
Divided Clock
Divided Clock
Master Clock
Master Clock
DIV = 3
DIV = 1
MCK
/ 2
Divided Clock Frequency = MCK/2
Divided Clock Frequency = MCK/6
Clock Divider
12-bit Counter
SSC_CMR
Divided Clock
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12