SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 466
SAM3N00A
Manufacturer Part Number
SAM3N00A
Description
Manufacturer
Atmel Corporation
- Current page: 466 of 752
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28.6
28.6.1
28.6.2
28.6.3
466
466
Product Dependencies
SAM3N
SAM3N
I/O Lines
Power Management
Interrupt
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer
must perform the following step:
The user must not program TWD and TWCK as open-drain. It is already done by the hardware.
Table 28-4.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the
programmer must first configure the PMC to enable the TWI clock.
The TWI interface has an interrupt line connected to the Nested Vector Interrupt Controller
(NVIC). In order to handle interrupts, the NVIC must be programmed before configuring the TWI.
Table 28-5.
• Program the PIO controller to dedicate TWD and TWCK as peripheral lines.
• Enable the peripheral clock.
Instance
Instance
TWI0
TWI1
TWI0
TWI0
TWI1
TWI1
I/O Lines
Peripheral IDs
19
20
ID
Figure 28-2 on page
TWCK0
TWCK1
Signal
TWD0
TWD1
465). When the bus is free, both lines are
I/O Line
PA3
PB5
PB4
PA4
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Peripheral
A
A
A
A
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