SAM3N00A Atmel Corporation, SAM3N00A Datasheet - Page 497
SAM3N00A
Manufacturer Part Number
SAM3N00A
Description
Manufacturer
Atmel Corporation
- Current page: 497 of 752
- Download datasheet (17Mb)
28.11.5
Name:
Addresses: 0x40018010 (0), 0x4001C010 (1)
Access:
Reset:
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
T
T
low
high
=
=
31
23
15
(
–
7
(
(
(
CLDIV
CHDIV
TWI Clock Waveform Generator Register
TWI_CWGR
Read-write
0x00000000
×
×
2
2
CKDIV
CKDIV
30
22
14
–
6
)
)
+
+
4 )
4 )
×
×
T
T
MCK
MCK
29
21
13
–
5
28
20
12
–
4
CHDIV
CLDIV
27
19
11
–
3
26
18
10
–
2
CKDIV
25
17
–
9
1
SAM3N
SAM3N
24
16
–
8
0
497
497
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