AD7952 Analog Devices, AD7952 Datasheet - Page 10

• Manufacturer Part Number: AD7952
• Manufacturer: Analog Devices

Specifications of AD7952

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p,Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7952
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Mnemonic
D9 or
RDERROR
D10 or
HW/SW
D11 or
SCIN
D12 or
SCCLK
D13 or
SCCS
BUSY
TEN
RD
CS
RESET
PD
CNVST
BIPOLAR
REF
REFGND
Type
DO
DI/O
DI/O
DI/O
DI/O
DO
DI
DI
DI
DI
DI
DI
DI
AI/O
AI
2
2
2
1
Description
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as
an incomplete data read error flag. If a data read is started and not completed when the current
conversion is completed, the current data is lost and RDERROR is pulsed high.
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7952 by hardware or software. See the Hardware Configuration section and Software
Configuration section.
When HW/SW = low, the AD7952 is configured through software using the serial configuration register.
When HW/SW = high, the AD7952 is configured through dedicated hardware input pins.
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low),
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low), this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends
on the logic state of the INVSCLK pin. See the Software Configuration section.
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low),
this input enables the serial configuration port. See the Software Configuration section.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low), the busy time changes according to Table 4.
Input Range Select. Used in conjunction with BIPOLAR per the following.
Input Range (V)
0 to 5
0 to 10
±5
±10
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock in slave serial mode (not used for serial configurable port).
Reset Input. When high, reset the AD7952. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register.
See the Digital Interface section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power-down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Input Range Select. See description for Pin 30.
Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled,
producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,
allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF
capacitor is required with or without the internal reference and buffer. See the Reference Decoupling
section.
Reference Input Analog Ground. Connected to analog ground plane.
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BIPOLAR
Low
Low
High
High
TEN
Low
High
Low
High