AD7952 Analog Devices, AD7952 Datasheet - Page 25

• Manufacturer Part Number: AD7952
• Manufacturer: Analog Devices

Specifications of AD7952

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p,Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 39, when BYTESWAP is low, the LSB byte is
output on D[7:0] and the MSB is output on D[13:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped; the
LSB is output on D[13:8] and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 14-bit data can
be read in two bytes on either D[13:8] or D[7:0]. This interface
can be used in both master and slave parallel reading modes.
SERIAL INTERFACE
The AD7952 has a serial interface (SPI-compatible) multiplexed
on the data pins D[13:0]. The AD7952 is configured to use the
serial interface when SER/ PAR is held high.
Data Interface
The AD7952 outputs 14 bits of data, MSB first, on the SDOUT
pin. This data is synchronized with the 14 clock pulses provided
on the SDCLK pin. The output data is valid on both the rising
and falling edge of the data clock.
Serial Configuration Interface
The AD7952 can be configured through the serial configuration
register only in serial mode, because the serial configuration
pins are also multiplexed on the data pins D[13:10]. See the
Hardware Configuration section and Software Configuration
section for more information.
PINS D[13:8]
BYTESWAP
PINS D[7:0]
CS
RD
HI-Z
HI-Z
Figure 39. 8-Bit and 14-Bit Parallel Interface
t
12
HIGH BYTE
LOW BYTE
t
12
LOW BYTE
HIGH BYTE
t
13
HI-Z
HI-Z
Rev. 0 | Page 25 of 32
MASTER SERIAL INTERFACE
The pins multiplexed on D[8:0] and used for master serial
interface are: DIVSCLK[0], DIVSCLK[1], EXT/ INT , INVSYNC,
INVSCLK, RDC, SDOUT, SDCLK, and SYNC.
Internal Clock (SER/ PAR = High, EXT/ INT = Low)
The AD7952 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/ INT pin is held low. The
AD7952 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK and the SYNC signals
can be inverted, if desired, using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data can
be read during the following conversion or after each conversion.
Figure 40 and Figure 41 show detailed timing diagrams of these
two modes.
Read During Convert (RDC = High)
Setting RDC = high allows the master read (previous
conversion result) during conversion mode. Usually, because
the AD7952 is used with a fast throughput, this mode is the
most recommended serial mode. In this mode, the serial clock
and data toggle at appropriate instances, minimizing potential
feedthrough between digital activity and critical conversion
decisions. In this mode, the SDCLK period changes because the
LSBs require more time to settle and the SDCLK is derived
from the SAR conversion cycle. In this mode, the AD7952
generates a discontinuous SDCLK of two different periods and
the host should use an SPI interface.
Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low allows the read after conversion mode.
Unlike the other serial modes, the BUSY signal returns low
after the 14 data bits are pulsed out and not at the end of the
conversion phase, resulting in a longer BUSY width (refer to
Table 4 for BUSY timing specifications). The DIVSCLK[1:0]
inputs control the SDCLK period and SDOUT data rate. As a
result, the maximum throughput cannot be achieved in this
mode. In this mode, the AD7952 also generates a discontinuous
SDCLK; however, a fixed period and hosts supporting both SPI
and serial ports can also be used.
AD7952