AD7952 Analog Devices, AD7952 Datasheet - Page 24

• Manufacturer Part Number: AD7952
• Manufacturer: Analog Devices

Specifications of AD7952

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p,Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7952
INTERFACES
DIGITAL INTERFACE
The AD7952 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7952
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
the OB/ 2C input pin, both twos complement or straight binary
coding can be used.
Two signals, CS and RD , control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7952 in
multicircuit applications and is held low in a single AD7952
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7952. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7952 and
clears the data bus and configuration register. See Figure 35 for
the RESET timing details.
PARALLEL INTERFACE
The AD7952 is configured to use the parallel interface when
SER/ PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 36 details the timing for this mode.
RESET
CNVST
BUSY
DATA
BUS
Figure 35. RESET Timing
t
9
t
8
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Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 37 and
Figure 38, respectively. When the data is read during the conver-
sion, it is recommended that it is read-only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CS = RD = 0
CNVST,
CNVST
BUSY
BUSY
DATA
BUSY
DATA
DATA
Figure 38. Slave Parallel Data Timing for Reading (Read During Convert)
BUS
BUS
BUS
Figure 36. Master Parallel Data Timing for Reading (Continuous Read)
Figure 37. Slave Parallel Data Timing for Reading (Read After Convert)
CS
RD
RD
CS = 0
t
t
t
3
12
3
t
12
PREVIOUS CONVERSION DATA
CONVERSION
PREVIOUS
CONVERSION
t
t
1
1
CURRENT
t
13
t
13
t
10
t
4
t
4
t
11
NEW DATA