AD7952 Analog Devices, AD7952 Datasheet - Page 23

• Manufacturer Part Number: AD7952
• Manufacturer: Analog Devices

Specifications of AD7952

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 10V p-p,20 V p-p,40 V p-p,Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

OVDD should be set to the same level as the system interface.
Sufficient decoupling is required, consisting of at least a 10 μF
capacitor and a 100 nF capacitor with the 100 nF capacitors
placed as close as possible to the AD7952.
Power Sequencing
The AD7952 is independent of power supply sequencing and is
very insensitive to power supply variations on AVDD over a wide
frequency range, as shown in Figure 32.
Power Dissipation vs. Throughput
In impulse mode, the AD7952 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 33). This feature makes the AD7952 ideal for very
low power, battery-operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails (that is, OVDD and OGND).
1000
100
10
80
75
70
65
60
55
50
45
40
35
30
1
10
1
WARP MODE POWER
IMPULSE MODE POWER
Figure 33. Power Dissipation vs. Sample Rate
Figure 32. AVDD PSRR vs. Frequency
100
10
EXT REF
INT REF
FREQUENCY (kHz)
1000
100
10000
PDREF = PDBUF = HIGH
1000
100000
1000000
10000
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Power Down
Setting PD = high powers down the AD7952, thus reducing
supply currents to their minimums, as shown in Figure 23. When
the ADC is in power-down, the current conversion (if any) is
completed and the digital bus remains active. To further reduce
the digital supply currents, drive the inputs to OVDD or OGND.
Power-down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a
don’t care and should be tied to either high or low.
CONVERSION CONTROL
The AD7952 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. A
detailed timing diagram of the conversion process is shown in
Figure 34. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
completed. The CNVST signal operates independently of the CS
and RD signals.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground, and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 27.
CNVST
MODE
BUSY
ACQUIRE
t
t
3
5
Figure 34. Basic Conversion Timing
t
1
CONVERT
t
7
t
4
t
2
t
6
ACQUIRE
t
8
AD7952
CONVERT