AD7492 Analog Devices, AD7492 Datasheet - Page 13

• Manufacturer Part Number: AD7492
• Description: 1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC
• Manufacturer: Analog Devices

Specifications of AD7492

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7492 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to V
12 shows a very simplified schematic of the ADC. The control
logic, SAR register, and capacitive DAC are used to add and
subtract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
Figure 13 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
Figure 14 shows the ADC during conversion. When conversion
starts, SW2 opens and SW1 moves to Position B, causing the
comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion result is available in
the SAR register.
AGND
AGND
CONTROL
V
V
INPUTS
IN
IN
V
REF
V
IN
SW1
SW1
A
A
IN
Figure 12. Simplified Block Diagram of AD7492
.
B
B
CAPACITIVE
SWITCHES
Figure 13. ADC Acquisition Phase
Figure 14. ADC Conversion Phase
DAC
SAR
CONTROL LOGIC
2kΩ
2kΩ
SW2
SW2
COMPARATOR
COMPARATOR
COMPARATOR
OUTPUT DATA
12-BIT PARALLEL
CONTROL LOGIC
CONTROL LOGIC
CAPACITIVE
CAPACITIVE
DAC
DAC
REF
. Figure
Rev. A | Page 13 of 24
TYPICAL CONNECTION DIAGRAM
Figure 15 shows a typical connection diagram for the AD7492.
Conversion is initiated by a falling edge on CONVST . Once
CONVST goes low the BUSY signal goes high, and at the end of
the conversion, the falling edge of BUSY is used to activate an
interrupt service routine. The CS and RD lines are then activated
in parallel to read the 12 data bits. The internal band gap
reference voltage is 2.5 V, providing an analog input range of 0 V
to 2.5 V, making the AD7492 a unipolar A/D. A capacitor with a
minimum capacitance of 100 nF is needed at the output of the
REF OUT pin as it stabilizes the internal reference value. It is
recommended to perform a dummy conversion after power-up as
the first conversion result could be incorrect. This also ensures
that the part is in the correct mode of operation. The CONVST
pin should not be floating when power is applied, as a rising edge
on CONVST might not wake up the part.
In Figure 15 the V
logic output voltage values being either 0 V or DV
voltage applied to V
logic signals and the input logic signals. For example, if DV
supplied by a 5 V supply and V
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, etc.). The LSB size equals 2.5/4096 for the
AD7492. The ideal transfer characteristic for the AD7492 is
shown in Figure 16.
µC/µP
2.5V
PARALLELED
INTERFACE
Figure 15. Typical Connection Diagram
DRIVE
DRIVE
1nF
100nF
pin is tied to DV
controls the voltage value of the output
10µF
V
DV
REF OUT
CS
CONVST
RD
BUSY
DB0 TO
DB9 (DB11)
DRIVE
DRIVE
DD
AD7492
+
AV
by a 3 V supply, the logic
DD
PS/FS
V
DD
IN
0.1µF
, which results in
+
0V TO 2.5V
47µF
DD
AD7492
. The
ANALOG
SUPPLY
2.7V TO 5.25V
DD
is