AD7492 Analog Devices, AD7492 Datasheet - Page 8

• Manufacturer Part Number: AD7492
• Description: 1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC
• Manufacturer: Analog Devices

Specifications of AD7492

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

AD7492
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
1 to 3,
13 to 18,
22 to 24
4
5
6
7
8
9
10
11
12
19
Mnemonic
DB11 to DB0
AV
REF OUT
V
AGND
CS
RD
CONVST
PS/FS
BUSY
DGND
IN
DD
Function
Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are
three-state outputs that are controlled by CS and RD. The output high voltage level for these outputs is
determined by the V
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492.
The AV
even on a transient basis. This supply should be decoupled to AGND.
Reference Out. The output voltage from this pin is 2.5 V ± 1%.
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents
a high dc input impedance.
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals
should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The
conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both
connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired
permanently low.
Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the
same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently
low, in which case the data bus is always active and the result of the new conversion is clocked out slightly
before to the BUSY line going low.
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The
conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is
determined by the PS/FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the
part. Wake-up time depends on the type of sleep mode.
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is
kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the
internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full
sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is
hardwired either high (DV
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns
to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY
goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode
on the falling edge of BUSY.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
DD
and DV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart,
DRIVE
(MSB) DB11
REF OUT
CONVST
input.
AGND
PS/FS
BUSY
DB10
AV
DD
DB9
V
RD
CS
DD
) or low (GND).
Figure 3. Pin Configuration
IN
10
11
12
Rev. A | Page 8 of 24
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD7492
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
DB8
DB7
DB6
V
DV
DGND
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DRIVE
DD