AD7492 Analog Devices, AD7492 Datasheet - Page 6

• Manufacturer Part Number: AD7492
• Description: 1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC
• Manufacturer: Analog Devices

Specifications of AD7492

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

AD7492
TIMING SPECIFICATIONS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
CONVERT
WAKEUP
1
2
3
4
5
6
7
8
9
10
Sample tested @ 25°C to ensure compliance. All input signals are specified with t
The AD7492-5 is specified with V
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
4
DD
4
5
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
= 2.7 V to 5.25 V, T
AD7492/AD7492-4
880
20
500
10
10
40
0
0
20
15
8
0
120
100
3
A
= T
DD
MIN
= 4.75 V to 5.25 V.
Limit at T
to T
MAX
, unless otherwise noted.
MIN
AD7492-5
680
20
500
10
10
N/A
0
0
20
15
8
0
120
100
Figure 2. Load Circuit for Digital Output Timing Specifications
, T
3
MAX
TO OUTPUT
2
PIN
50pF
Rev. A | Page 6 of 24
C
L
ns max
μs max
ns max
ns max
ns min
Unit
μs max
ns min
ns max
ns max
ns min
ns min
ns max
ns max
ns min
1
200µA
200µA
R
= t
F
= 5 ns (10% to 90% of V
I
I
OL
OH
Description
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST Pulse Width
CONVST to BUSY Delay, V
CONVST to BUSY Delay, V
BUSY to CS Setup Time
CS to RD Setup Time
RD Pulse Width
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
1.6V
7
, quoted in the timing characteristics is the true bus relinquish
DD
) and timed from a voltage level of 1.6 V (see Figure 2).
DD
DD
= 5 V
= 3 V