AD7492 Analog Devices, AD7492 Datasheet - Page 19

• Manufacturer Part Number: AD7492
• Description: 1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC
• Manufacturer: Analog Devices

Specifications of AD7492

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

ADSP-21065Lto AD7492 Interface
Figure 30 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC® processor. This interface is an example
of one of three DMA handshake modes. The MS
actually three memory select lines. Internal ADDR25–24 are
decoded into MS
The DMAR
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
TMS320C25 to AD7492 Interface
Figure 31 shows an interface between the AD7492 and the
TMS320C25. The CONVST signal can be applied from the
TMS320C25 or from an external source. The BUSY line
interrupts the digital signal processor when conversion is
completed. The TMS320C25 does not have a separate RD
output to drive the AD7492 RD input directly. This has to be
generated from the processor STRB and R/ W outputs with the
addition of some glue logic. The RD signal is OR-gated with the
MSC signal to provide the WAIT state required in the read cycle
for correct interface timing. The following instruction is used to
read the conversion from the AD7492:
where:
D is the data memory address.
ADC is the AD7492 address.
The read operation must not be attempted during conversion.
IN D,ADC
ADSP-21065L
ADDR
D0 TO 31
ADDR
DMAR
1
(DMA Request 1) is used in this setup as the
0
MS
Figure 30. ADSP-21065L to AD7492 Interface
RD
TO
1
23
ADDITIONAL PINS OMITTED FOR CLARITY.
X
1
1
3-0
, these lines are then asserted as chip selects.
ADDRESS BUS
ADDRESS
DECODER
ADDRESS
DATA BUS
LATCH
ADDRESS
BUS
CS
BUSY
RD
DB0 TO DB9
(DB11)
OPTIONAL
AD7492
X
CONVST
control line is
Rev. A | Page 19 of 24
PIC17C4x to AD7492 Interface
Figure 32 shows a typical parallel interface between the AD7492
and PIC17C4x. The microcontroller sees the ADC as another
memory device with its own specific memory address on the
memory map. The CONVST signal can be controlled by either
the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a
conversion ends. The INT pin on the PIC17C4x must be
configured to be active on the negative edge. Port C and Port D
of the microcontroller are bidirectional and used to address the
AD7492 and to read in the 12-bit data. The OE pin on the PIC
can be used to enable the output buffers on the AD7492 and
perform a read operation.
PIC17C4x
DMD0 TO DMD15
AD0 TO AD15
TMS320C25
A0 TO A15
1
ALE
READY
INT
OE
STRB
MSC
R/W
1
Figure 31. TMS320C25 to AD7492 Interface
1
ADDITIONAL PINS OMITTED FOR CLARITY.
1
IS
Figure 32. PIC17C4x to AD7492 Interface
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
DECODER
DATA BUS
ADDRESS
ADDRESS
LATCH
ADDRESS
DECODER
CS
BUSY
RD
DB0 TO DB9
(DB11)
OPTIONAL
AD7492
DB0 TO DB9
(DB11)
CONVST
CS
RD
BUSY
AD7492
OPTIONAL
CONVST
AD7492