AD7711A Analog Devices, AD7711A Datasheet - Page 21

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the DRDY line, and the write operation does not have any effect
on the status of DRDY. A write operation to the control register
or the calibration register must always write 24 bits to the
respective register.
Figure 11 shows a write operation to the AD7711A. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must
remain valid for the duration of the serial write operation. The
falling edge of TFS enables the internally generated SCLK
output. The serial data to be loaded to the AD7711A must be
valid on the rising edge of this SCLK signal. Data is clocked
into the AD7711A on the rising edge of the SCLK signal, with
the MSB transferred first. On the last active high time of SCLK,
the LSB is loaded to the AD7711A. Subsequent to the next
falling edge of SCLK, the SCLK output is turned off. (The
timing diagram of Figure 11 assumes a pull-up resistor on the
SCLK line.)
External Clocking Mode
The AD7711A is configured for its external clocking mode by
tying the MODE pin low. In this mode, SCLK of the AD7711A
is configured as an input, and an external serial clock must be
provided to this SCLK pin. This external clocking mode is
designed for direct interface to systems that provide a serial
clock output that is synchronized to the serial data output,
including microcontrollers such as the 80C51, 87C51, 68HC11,
and 68HC05 and most digital signal processors.
REV. D
Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation
SDATA (O)
SCLK (O)
TFS (I)
A0 (I)
t
14
t
t
16
18
MSB
t
19
–21–
t
9
Read Operation
As with the self-clocking mode, data can be read from either the
output register, the control register, or the calibration registers.
A0 determines whether the data read accesses data from the
control register or from the output/calibration registers. This A0
signal must remain valid for the duration of the serial read
operation. With A0 high, data is accessed from either the output
register or from the calibration registers. With A0 low, data is
accessed from the control register.
The function of the DRDY line is dependent on only the output
update rate of the device and the reading of the output data
register. DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the DRDY line will
remain low. The output register will continue to be updated at
the output update rate, but DRDY will not indicate this. A read
from the device in this circumstance will access the most recent
word in the output register. If a new data-word becomes avail-
able to the output register while data is being read from the
output register, DRDY will not indicate this, and the new data-
word will be lost to the user. DRDY is not affected by reading
from the control register or the calibration register.
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low while DRDY is high, no data
transfer will take place. DRDY does not have any effect on reading
data from the control register or from the calibration registers.
t
10
LSB
t
17
t
15
AD7711A
2