AD7711A Analog Devices, AD7711A Datasheet - Page 5

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
Self-Clocking Mode
NOTES
1
2
3
4
5
6
REV. D
CLK IN
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 10 to 13.
The AD7711A is specified with a 10 MHz clock for AV
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device
The AD7711A is production tested with f
Specified using 10% and 90% points on waveform of interest.
CLK IN LO
CLK IN HI
r
f
1
than 10.5 V.
can draw higher current than specified and possibly become uncalibrated.
6
6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
3
4
5
6
7
8
9
10
14
15
16
17
18
19
7
7
4, 5
Limit at T
(A, S Versions)
400
10
8
0.4 ¥ t
0.4 ¥ t
50
50
1000
0
0
2 ¥ t
0
4 ¥ t
4 ¥ t
t
t
t
3 ¥ t
50
0
4 ¥ t
4 ¥ t
0
10
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
/2
/2 + 30
/2
CLK IN
/2
+ 20
+ 20
+ 20
MIN
, T
at 10 MHz (8 MHz for AV
1, 2
MAX
DD
(DV
= 0 V; f
voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV
DD
= +5 V
CLKIN
Unit
kHz min
MHz max
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
5%; AV
DD
> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
–5–
DD
= +5 V or +10 V
Conditions/Comments
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
AV
AV
Master Clock Input Low Time. t
Master Clock Input High Time
SYNC Pulse Width
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
DD
DD
= 5 V ± 5%
= 5.25 V to 10.5 V
3
,
5%; V
SS
= 0 V or –5 V
DD
, unless otherwise noted.)
DD
voltages greater than 5.25 V and less
CLK IN
= 1/f
10%; AGND = DGND
CLK IN
AD7711A
2