AD7711A Analog Devices, AD7711A Datasheet - Page 26

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
MOV SCON,#00000000B;
MOV IE,#10010000B;
MOV IP,#00010000B;
SETB 91H;
SETB 90H;
MOV R1,#003H;
MOV R0,#030H;
MOV A,#00H;
MOV SBUF,A;
WAIT:
JMP WAIT;
INT ROUTINE:
NOP;
MOV A,R1;
JZ FIN;
DEC R1;
MOV A,@R;
INC R0;
RLC A;
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C:MOV A,B;
CLR 93H;
CLR 91H;
MOV SBUF,A;
RETI;
FIN:
SETB 91H;
SETB 93H;
RETI;
Table VIII. 8XC51 Code for Writing to the AD7711A
Enable Transmit Interrupt
Prioritize the Transmit Interrupt
Sets Number of Bytes to Be Written
Start Address in RAM for Bytes
Interrupt Subroutine
If Zero Jump to FIN
Move Byte into the Accumulator
Bring A0 Low
Write to Serial Port
Return from Subroutine
Set A0 High
Return from Interrupt Subroutine
Configure 8051 for MODE 0
Operation & Enable Serial Reception
Bring TFS High
Bring RFS High
in a Write Operation
Clear Accumulator
Initialize the Serial Port
Wait for Interrupt
Load R1 to Accumulator
Decrement R1 Byte Counter
Increment Address
Rearrange Data—From LSB First
to MSB First
Bring TFS Low
Set TFS High
–26–
AD7711A to 68HC11 Interface
Figure 18 shows an interface between the AD7711A and the
68HC11 microcontroller. The AD7711A is configured for its
external clocking mode while the SPI port is used on the 68HC11,
which is in its single chip mode. The DRDY line from the
AD7711A is connected to the Port PC2 input of the 68HC11,
so the DRDY line is polled by the 68HC11. The DRDY line
can be connected to the IRQ input of the 68HC11 if an inter-
rupt driven system is preferred. The 68HC11 MOSI and MISO
lines should be configured for wired-OR operation. Depending
on the interface configuration, it may be necessary to provide
bidirectional buffers between the 68HC11 MOSI and MISO
lines.
The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 0 and its CPHA bit set to a Logic 1. With a
10 MHz master clock on the AD7711A, the interface will oper-
ate with all four serial clock rates of the 68HC11.
68HC11
Figure 18. AD7711A to 68HC11 Interface
MISO
MOSI
SCK
PC2
PC0
PC3
PC1
SS
DV
DD
DV
DD
SYNC
RFS
TFS
DRDY
A0
SCLK
SDATA
MODE
AD7711A
REV. D