AD9148 Analog Devices, AD9148 Datasheet - Page 49

• Manufacturer Part Number: AD9148
• Manufacturer: Analog Devices

Specifications of AD9148

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 59. The sampling point of the data bus nominally occurs
250 ps after each edge of the DCI signal and has an uncertainty of
± 250 ps when the DCI delay is set to 00b (Register 0x72[1:0]),
as illustrated by the sampling interval. The data and FRAME
signals must be valid throughout this sampling interval. The data
and FRAME signals may change at any time between sampling
intervals.
The setup (t
shown in Figure 59. The minimum setup and hold times are
shown in Table 16.
Table 16. Data Port Setup and Hold Times
DCI Delay
(Register 0x72, Bits[1:0])
00
01
10
11
The data interface timing can be verified by using the SED
circuitry. See the Interface Timing Validation section for details.
In data rate mode with synchronization enabled, a second timing
constraint between DCI and DACCLK must be met in addition
to the DCI-to-data timing shown in Table 17. In data rate mode,
only one FIFO slot is being used. The DCI to DACCLK timing
restriction is required to prevent data being written to and read
from the FIFO slot at the same time. The required timing
between DCI and DACCLK is shown in Figure 58.
S
) and hold (t
H
) times with respect to the edges are
Minimum Setup
Time, t
−0.02
−0.16
−0.28
−0.36
DATA
DCI
S
(ns)
Minimum Hold
Time, t
0.52
0.78
1.03
1.16
Figure 59. Timing Diagram for Input Data Ports
SAMPLING
INTERVAL
H
t
DATA
(ns)
Rev. B | Page 49 of 72
t
S
Table 17. DCI to DACCLK Setup and Hold Times vs. DCI
Delay Value
DCI Delay
(Register 0x72,Bits[1:0])
00
01
10
11
Figure 58. Timing Diagram for Input Data Port (Data Rate Mode with Sync On)
DACCLK/
REFCLK
SAMPLING
t
INTERVAL
H
DCI
SAMPLING
t
INTERVAL
SDCI
t
HDCI
t
DATA
Minimum Setup
Time, t
−0.06
−0.22
−0.36
−0.45
SDCI
(ns)
Minimum Hold
Time, t
0.85
1.14
1.43
1.59
AD9148
HDCI
(ns)