AD9148 Analog Devices, AD9148 Datasheet - Page 57

• Manufacturer Part Number: AD9148
• Manufacturer: Analog Devices

Specifications of AD9148

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
Table 25. PLL Settings
PLL SPI Control
PLL Loop Bandwidth
PLL Control 1 Register
PLL Cross Control Enable
CLOCK MULTIPLICATION
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference clock.
When the PLL clock multiplier is enabled (Register 0x0A[7] = 1),
the clock multiplication circuit generates the DAC sample clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 74.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f
frequency multiplied by N0 × N1.
The DAC sample clock frequency, f
The output frequency of the VCO must be chosen to keep f
the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency
of the reference clock and the values of N1 and N0 must be chosen
so that the desired DACCLK frequency can be synthesized and
the VCO output frequency is in the correct range.
PLL Bias Settings
There are four bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 25 are the recommended settings for these parameters.
Configuring the VCO Tuning Band
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.
For any desired VCO output frequency, there may be several
valid PLL band select values. The frequency bands of a typical
device are shown in Figure 75. Device-to-device variations and
operating temperature affect the actual band frequency range.
f
f
VCO
DACCLK
= f
REFCLK
= f
REFCLK
× (N0 × N1)
× N1
VCO
, equal to the REFCLK input signal
REFCLK_P/REFCLK_N
(PIN B9 AND PIN A9)
PC_CLK
÷N2
DACCLK
0x0D[7:6]
N2
, is equal to
(PIN B6 AND PIN A6)
CLK_P/CLK_N
Figure 74. PLL Clock Multiplication Circuit
PLL LOCK LOST
DETECTION
VCO
PLL LOCK
Register
0x0C
0x0C
0x0D
0x06[7:6]
PHASE
PLL ENABLE
in
Rev. B | Page 57 of 72
0x0D[1:0]
0x0A[7]
÷N1
N1
FILTER
LOOP
Therefore, it is required that the optimal PLL band select value
be determined for each individual device.
Automatic VCO Band Select
The device has an automatic VCO band select feature on chip;
using this feature is a simple and reliable method for configuring
the VCO frequency band. To use the automatic VCO band select
feature, enable the PLL by writing 0xC0 to Register 0x0A and
enable the auto band select mode by writing 0x80 to Register 0x0A.
When this value is written, the device executes an automated
routine that determines the optimal VCO band setting for the
device. The setting selected by the device ensures that the PLL
remains locked over the full −40°C to +85°C operating temperature
range of the device without further adjustment. (The PLL remains
locked over the full temperature range even if the temperature
during initialization is at one of the temperature extremes.)
0x0D[3:2]
÷N0
Address
N0
Figure 75. PLL Lock Range Overtemperature for a Typical Device
12
16
20
24
28
32
36
40
44
48
52
56
60
0
4
8
1000
ADC
VCO
Bit
[7:5]
[4:0]
[4]
1200
DACCLK
0x0E[3:0]
PLL CONTROL
VOLTAGE
1400
VCO FREQUENCY (MHz)
1600
Optimal Setting
110
01001
1
1800
2000
AD9148
2200