CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 40

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

11.15 Receiver Error (16) (Read Only)
UNLOCK
V
CONF
BIP
PAR
11.16 Receiver Error Mask (17)
40
7
0
7
0
This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occur-
rence of the error, and will stay high until the register is read. Reading the register resets all bits to 0,
unless the error source is still true. Bits that are masked off in the receiver error mask register will
always be 0 in this register. This register defaults to 00.
QCRCQ-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.
0 - No error
1 - Error
CCRCChannel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.
This bit is valid in professional mode only.
0 - No error
1 - Error
The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a
mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the
receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the cur-
rent audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is con-
sidered masked, meaning that its occurrence will not appear in the receiver error register, will not
affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample.
The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio
sample even when unmasked. This register defaults to 00.
QCRCM
QCRC
0 - PLL locked
1 - PLL out of lock
0 - Data is valid and is normally linear coded PCM audio
1 - Data is invalid, or may be valid compressed audio
0 - No error
1 - Confidence error. This indicates that the received data eye opening is less than
0 - No error
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
0 - No error
1 - Parity error
PLL lock status bit. Updated on CS block boundaries.
Received AES3 Validity bit status. Updated on sub-frame boundaries.
Confidence bit. Updated on sub-frame boundaries.
Bi-phase error bit. Updated on sub-frame boundaries.
Parity bit. Updated on sub-frame boundaries.
6
6
half a bit period, indicating a poor link that is not meeting specifications.
CCRCM
CCRC
5
5
UNLOCKM
UNLOCK
4
4
VM
3
V
3
CONFM
CONF
2
2
BIPM
BIP
1
1
CS8420
DS245PP2
PARM
PAR
0
0