AD5425 Analog Devices, AD5425 Datasheet - Page 16

• Manufacturer Part Number: AD5425
• Description: High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5425

• Resolution (bits): 8bit
• Dac Update Rate: 2.47MSPS
• Dac Settling Time: 100ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5425
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
In the current mode circuit of Figure 32, I
is biased positive by an amount applied to V
configuration, the output voltage is given by
As D varies from 0 to 255, the output voltage varies from
V
sourcing all possible variations in current at the I
without any problems.
It is important to note that V
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result, their on resistance differs and
this degrades the linearity of the DAC.
Voltage Switching Mode of Operation
Figure 33 shows this DAC operating in the voltage switching
mode. The reference voltage V
I
at the V
voltage results in a positive output voltage, making single-
supply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
OUT
BIAS
V
2 is connected to AGND, and the output voltage is available
IN
V
V
should be a low impedance source capable of sinking and
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE
OUT
OUT
REF
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
= [D × (R
= V
terminal. In this configuration, a positive reference
Figure 32. Single-Supply Current Mode Operation
V
REF
BIAS
to V
GND
V
V
FB
DD
DD
/R
OUT
V
DAC
BIAS
= 2V
R
) × (V
FB
IN
I
I
OUT
OUT
BIAS
IN
is limited to low voltages because
BIAS
1
2
is applied to the I
− V
− V
IN
C1
IN
)] + V
OUT
A1
A1
BIAS
2 and hence I
. In this
BIAS
OUT
OUT
2 terminal
V
1 pin,
OUT
OUT
Rev. A | Page 16 of 28
1
It is important to note that V
the switches in the DAC ladder no longer have the same source
drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC.
V
internal diode turns on, exceeding the maximum ratings of the
device. In this type of application, the full range of the DAC
multiplying capability is lost.
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting
amplifier because of the resistor tolerance errors. To generate a
negative reference, the reference can be level shifted by an
op amp such that the V
become the virtual ground and −2.5 V respectively, as shown
in Figure 34.
IN
V
IN
+5V
–5V
must also not go negative by more than 0.3 V, otherwise an
Figure 34. Positive Voltage Output with Minimum of Components
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
V
Figure 33. Single-Supply Voltage Switching Mode Operation
OUT
ADR03
GND
NOTES:
1
2
ADDITIONAL PINS OMITTED FOR CLARITY.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
–2.5V
V
I
I
IN
OUT
OUT
1
2
R
V
FB
REF
V
DD
V
GND
OUT
DD
GND
V
V
= 5V
DD
DD
and GND pins of the reference
IN
R
V
is limited to low voltage because
FB
REF
I
I
OUT
OUT
1
2
R1
C1
A1
R2
A1
V
OUT
= 0V TO +2.5V
V
OUT
REF