AD5425 Analog Devices, AD5425 Datasheet - Page 19

• Manufacturer Part Number: AD5425
• Description: High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5425

• Resolution (bits): 8bit
• Dac Update Rate: 2.47MSPS
• Dac Settling Time: 100ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

SERIAL INTERFACE
The AD5425 has a simple 3-wire interface that is compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards.
Data is written to the device in 8-bit words. This 8-bit word
consists of 8 data bits, as shown in Figure 37.
SYNC is an edge-triggered input that acts as a frame synchro-
nization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling to SCLK falling edge setup time, t
After loading eight data bits to the shift register, the SYNC line
is brought high. The contents of the DAC register and the
output are updated by bringing LDAC low any time after the
8-bit data transfer is complete, as seen in the timing diagram of
Figure 2. LDAC can be tied permanently low if required. For
another serial transfer to take place, the interface must be
enabled by another falling edge of SYNC .
Low Power Serial Interface
To minimize the power consumption of the device, the interface
fully powers up only when the device is being written to, that is,
on the falling edge of SYNC . The SCLK and SDIN input buffers
are powered down on the rising edge of SYNC .
MICROPROCESSOR INTERFACING
Microprocessor interfacing to this DAC is via a serial bus that
uses standard protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire inter-
face consisting of a clock signal, a data signal, and a synchro-
nization signal. An LDAC pin is also included. The AD5425
requires an 8-bit word with the default being data valid on the
falling edge of SCLK, but this is changeable via the control bits
in the data-word.
ADSP-21xx-to AD5425 Interface
The ADSP-21xx family of DSPs is easily interfaced to this
family of DACs without extra glue logic. Figure 38 shows an
example of an SPI interface between the DAC and the ADSP-
2191. SCK of the DSP drives the serial data line, DIN. SYNC is
driven from one of the port lines, in this case SPIxSEL .
DB7 (MSB)
DB7 DB6 DB5 DB4 DB3 DB2
Figure 37. 8-Bit Input Shift Register Contents
DATA BITS
DB1
4
DB0 (LSB)
.
DB0
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A serial interface between the DAC and DSP SPORT is shown
in Figure 39. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications from one device to
the other are compatible: frame sync delay and frame sync setup
and hold, data delay and data setup and hold, and SCLK width.
The DAC interface expects a t
falling edge setup time) of 13 ns minimum. Consult the ADSP-
21xx user manual for information on clock and frame sync
frequencies for the SPORT register.
Table 10. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
1
1
Figure 39. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5425 Interface
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2101/
ADSP-2103/
ADSP-2191
ADSP-2191
SPIxSEL
1
Figure 38. ADSP-2191 SPI-to-AD5425 Interface
SCLK
MOSI
1
1
00
1
1
1
0111
Setting
1
SCK
TFS
DT
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
8-bit data-word
4
(SYNC falling edge to SCLK
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5425
AD5425
AD5425
1
1