AD8011 Analog Devices, AD8011 Datasheet - Page 14

• Manufacturer Part Number: AD8011
• Description: 300 MHz, 1 mA Current Feedback Amplifier
• Manufacturer: Analog Devices

Specifications of AD8011

• -3db Bandwidth: 400MHz
• Slew Rate: 3.5kV/µs
• Vos: 2mV
• Ib: 5µA
• # Opamps Per Pkg: 1
• Input Noise (nv/rthz): 2nV/rtHz
• Vcc-vee: 3V to 12V
• Isy Per Amplifier: 1.3mA
• Packages: DIP,SOIC

AD8011
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8011 requires
careful attention to board layout and component selection. Table I
shows the recommended component values for the AD8011.
Proper R
tion are mandatory.
Gain
–1
–2
–10
+1
+2
+10
+6
+6
R
output impedance.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 15). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional tan-
talum electrolytic capacitor (4.7 µF – 10 µF) should be connected
in parallel.
T
chosen for 50 Ω characteristic input impedance. R
Table I. Typical Bandwidth vs. Gain Setting Resistors
F
R
1000
1000
499
1000
1000
422
1000
500
design techniques and low parasitic component selec-
F
( )
R
1000
499
49.9
1000
47.5
200
100
G
( )
R
52.3
54.9
49.9
49.9
49.9
49.9
49.9
T
( )
O
Small Signal
–3 dB BW (MHz),
V
150
130
140
400
250
100
70
170
chosen for characteristic
S
=
5 V
–14–
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly
terminated at each end.
Figure 15. Inverting and Noninverting Configurations
V
V
IN
IN
R
T
R
R
R
G
T
G
NONINVERTING CONFIGURATION
INVERTING CONFIGURATION
R
R
F
F
C1
0.01 F
C2
0.01 F
C1
0.01 F
C2
0.01 F
R
R
O
O
C3
10 F
C4
10 F
C3
10 F
C4
10 F
V
+V
–V
V
+V
–V
OUT
OUT
S
S
S
S
REV. C