ADM1060 Analog Devices, ADM1060 Datasheet - Page 23

• Manufacturer Part Number: ADM1060
• Description: Multi Power Supply Sequencer & Supervisor
• Manufacturer: Analog Devices

Specifications of ADM1060

• # Supplies Monitored: 7
• Volt Monitoring Accuracy: 2.5%
• # Output Drivers: 9
• Fet Drive/enable Output: Both
• Package: 28 ld TSSOP

The control bits for these macrocells are stored locally in latches
that are loaded at power-up. These latches can also be updated
via the serial interface. The registers containing the macrocell
control bits and the function of each bit are defined in the tables
that follow.
Figure 21 highlights all 21 inputs to a given function and the
register/bits that need to be set in order to condition the 21
inputs correctly. The diagram only shows function A of Pro-
grammable Logic Block 1 (PLB1), but all functions are
programmed in the same way.
For example, if the user wishes to assert PLBOUT 200 ms after
all of the supplies are in spec (PLBOUT may be used to drive
the enable pin of an LDO), the supply fault detectors VBn, VH,
and VPn are required to control the function. The function is
programmed as follows:
Table 28. Programmable Logic Block Array (PLBA) Registers
Hex
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
10
11
12
13
14
Table
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 29
Table 30
Table 31
Table 32
Table 29
Table 30
Table 31
Table 32
Table 33
Name
P1PLBPOLA
P1PLBIMKA
P1SFDPOLA
P1SFDIMKA
P1GPIPOL
P1GPIIMK
P1WDICFG
PS1EN
P1PLBPOLB
P1PLBIMKB
P1SFDPOLB
P1SFDIMKB
P2PLBPOLA
P2PLBIMKA
P2SFDPOLA
P2SFDIMKA
P2GPIPOL
Default Power-
On Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Polarity sense for all eight other PLB outputs when used as inputs to the
A function of PLB1
Ignore mask for all eight other PLB outputs when used as inputs to the A
function of PLB1
Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A
function of PLB1
Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A
function of PLB1
Polarity sense and ignore mask bits for all four GPIs when used as inputs
to the A function of PLB1
Polarity sense and ignore mask bits for all four GPIs when used as inputs
to the B function of PLB1
Polarity sense and ignore mask bits for the pulsed and latched outputs of
the watchdog detector when used as inputs to both A and B functions of
PLB1
Enable bits for A and B functions of PLB1, polarity bit for PLB1 output
Polarity sense for all eight other PLB outputs when used as inputs to the
B function of PLB1
Ignore mask for all eight other PLB outputs when used as inputs to the B
function of PLB1
Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B
function of PLB1
Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the B
function of PLB1
Polarity sense for all eight other PLB outputs when used as inputs to the
A function of PLB2
Ignore mask for all eight other PLB outputs when used as inputs to the A
function of PLB2
Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A
function of PLB2
Ignore mask for all seven SFD inputs (VH, two VBs, four VPs) to the A
function of PLB2
Polarity sense and ignore mask bits for all four GPIs when used as inputs
to the A function of PLB2
Description
Rev. B | Page 23 of 52
1.
2.
3.
4.
The IGNORE bit of all the other inputs (GPIs, PDBs, WDI)
in the relevant P1xxxIMK registers is set to 1. Thus, regard-
less of its status, the input to the function AND gate for
these inputs will be 1.
Since the SFDs assert a 1 under a fault condition and a 0
when the supplies are in tolerance, the SFD outputs need to
be inverted before being applied to the function. Thus the
relevant bit in the P1SFDPOL register is set (see Table 38).
The function is enabled ( B it 1 of R egister P1EN—see
Table 36).
A rise time of 200 ms is programmed (register
P1PDBTIM—see register map for details).
ADM1060