ADM1060 Analog Devices, ADM1060 Datasheet - Page 41

• Manufacturer Part Number: ADM1060
• Description: Multi Power Supply Sequencer & Supervisor
• Manufacturer: Analog Devices

Specifications of ADM1060

• # Supplies Monitored: 7
• Volt Monitoring Accuracy: 2.5%
• # Output Drivers: 9
• Fet Drive/enable Output: Both
• Package: 28 ld TSSOP

Table 55. List of Configuration Update Registers
Hex Addr.
90
Table 56. Bit Map for UPDCFG Register 0x90 (Power-On Default 0x00)
Bit
7–4
3
2
1
0
INTERNAL REGISTERS
The ADM1060 contains a large number of data registers. A brief
description of the principal registers is given below. More
detailed descriptions are given in the relevant sections of this
data sheet.
Address Pointer Register. This register contains the address
that selects one of the other internal registers. When writing to
the ADM1060, the first byte of data is always a register address,
which is written to the Address Pointer register.
Name
Reserved
EE_ERASE
EEPROMLD
RAMLD
UPD
POWER-UP
(V
CC
EEPROM
>2.5V)
Table
Table 56
EEPROMLD
R/W
N/A
R/W
W
W
R/W
Name
UPDCFG
Description
Cannot be used
If set high, EEPROM page erasure can be programmed.
If set high, the ADM1060 will download the contents of its EEPROM to the RAM registers. This bit
self-clears (returns to 0) after the download.
If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit
self-clears (returns to 0) after the download.
If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM
register via the SMBus.
Default Power-
On Value
0x00
CONTROLLER
DATA
DEVICE
SMBus
Figure 24. Configuration Update Flow Diagram
LATCH A
Description
Configuration Update Control register for changing configuration of the
ADM1060 after power-up
Rev. B | Page 41 of 52
RAMLD
Configuration Registers. These registers provide control and
configuration for various operating parameters of the
ADM1060.
Polarity Registers. These registers define the polarity of inputs
to the PLBA.
Mask Registers. These registers allow masking of individual
inputs to the PLBA and masking of faults in the fault reporting
registers.
UPD
LATCH B
FUNCTION (E.G.,
OV THRESHOLD
ON VP1)
ADM1060