ADUC824 Analog Devices, ADUC824 Datasheet - Page 24

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

ADuC824
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general-
purpose register banks, reside in the SFR area. The SFR registers
include control, configuration, and data registers that provide
an interface between the CPU and all on-chip peripherals.
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
MDO
RDY0
PRE3
ISPI
SM0
TF2
TF1
CY
RD
EA
SFR MAP KEY:
SFR NOTE:
SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE.
CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES.
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
FEH
F6H
EEH
DEH
D6H
CEH
C6H
BEH
B6H
AEH
A6H
9EH
96H
8EH
86H
E6H
WCOL
PADC
EADC
EXF2
MDE
PRE2
SM1
RDY1
TR1
AC
WR
0
0 F5H
0
0 E5H
0
0
0
0
0
1
0
1
0
1 95H
0
1 85H
BIT MNEMONIC
BIT BIT ADDRESS
DEFAULT BIT VALUE
FDH
EDH
DDH
D5H
CDH
C5H
BDH
B5H
ADH
A5H
9DH
8DH
RCLK
MCO
SPE
PRE1
SM2
CAL
PT2
ET2
TF0
F0
T1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
FCH
F4H
ECH
E4H
NOXREF
DCH
D4H
CCH
C4H
BCH
B4H
ACH
A4H
9CH
94H
8CH
84H
SPIM
TCLK
PRE0
REN
MDI
TR0
RSI
PS
ES
T0
0
0 F3H
0
0 E3H
0
0
0
1
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
EBH
DBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
CPOL
EXEN2
I2CM
ERR0
THESE BITS ARE CONTAINED IN THIS BYTE.
WDIR
INT1
RS0
TB8
PT1
ET1
IE1
0
0 F2H
0
0 E2H
0
0
0
0
0
1
0
1 A2H
0
1 92H
0
1 82H
89H
FAH
EAH
DAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS
INT0
RB8
IE0
ERR1
WDS
PX1
EX1
TR2
OV
IT1
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
88H
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
A1H
99H
91H
89H
81H
SPR1
I2CTX
CNT2
T2EX
IT0
WDE
PT0
TXD
ET0
IE0
T1
FI
0
0
0 F0H
0
0 E0H
0 D8H
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
E8H
D0H
C8H
C0H
B8H
B0H
A8H
98H
90H
88H
WDWR
CAP2
I2CI
PX0
RXD
EX0
SPR0
IT0
R1
T2
P
88H
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
TCON
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
00H
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
E8H
E0H
D8H
D0H
C0H
B8H
B0H
A8H
A0H
F8H
F0H
C8H
98H
90H
88H
80H
ADCSTAT
SPICON
I2CCON
WDCON
T2CON
SCON
TCON
ACC
PSW
P3
P2
P1
P0
IP
IE
B
00H
00H
00H
00H
00H
10H
00H
FFH
00H
FFH
00H
FFH
00H
FFH
04H
00H
Figure 17 shows a full SFR memory map and SFR contents on
RESET NOT USED indicates unoccupied SFR locations. Unoc-
cupied locations in the SFR address space are not implemented;
i.e., no register exists at this location. If an unoccupied location
is read, an unspecified value is returned. SFR locations reserved
for future use are shaded (RESERVED) and should not be
accessed by user software.
RESERVED RESERVED
RESERVED
RESERVED
RESERVED
NOT USED
E9H
E1H
D9H
ADCMODE
D1H
B9H
NOT USED
A9H
A1H
99H
89H
81H
TIMECON
GN0L
ADC0L
OF0L
ECON
TMOD
SBUF
IEIP2
SP
A0H
55H
00H
00H
00H
00H
00H
00H
00H
07H
RESERVED
RESERVED
RESERVED RESERVED
NOT USED
NOT USED
EAH
DAH
D2H
CAH
C2H
A2H
9AH
8AH
E2H
ADC0CON
82H
RCAP2L
HTHSEC
GN0M
OF0M
ADC0M
I2CDAT
CHIPID
DPL
TL0
55H
00H
00H
07H
00H
06H
00H
00H
00H
00H
RESERVED
RESERVED
EBH
DBH
D3H
CBH
A3H
8BH
FBH
NOT USED
E3H
ADC1CON
NOT USED
9AH
83H
NOT USED
RCAP2H
ADC0H
I2CDAT
GN0H
OF0H
DACL
SEC
DPH
TL1
53H
80H
00H
00H
00H
00H
00H
00H
00H
00H
RESERVED
RESERVED
FCH
NOT USED
RESERVED
ECH
DCH
CCH
BCH
E4H
D4H
A4H
NOT USED
NOT USED
8CH
84H
EDATA1
ADC1L
DACH
GN1L
OF1L
DPP
TL2
MIN
TH0
SF
00H
9AH
00H
00H
45H
00H
00H
00H
00H
00H
RESERVED
RESERVED
RESERVED
EDH
DDH
CDH
BDH
RESERVED
RESERVED
FDH
E5H
D5H
A5H
NOT USED
NOT USED
8DH
DACCON
EDATA2
ADC1H
GN1H
OF1H
HOUR
ICON
TH2
TH1
00H
59H
80H
00H
00H
00H
00H
00H
00H
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED RESERVED
RESERVED
RESERVED RESERVED
RESERVED RESERVED
RESERVED
NOT USED
NOT USED
BEH
C6H
A6H
EDATA3
EADRL
INTVAL
00H
00H
00H
RESERVED
RESERVED
RESERVED
RESERVED
NOT USED
NOT USED
NOT USED
NOT USED
F7H
DFH
D7H
BFH
87H
PSMCON
PLLCON
EDATA4
SPIDAT
PCON
DEH
00H
03H
00H
00H