ADUC824 Analog Devices, ADUC824 Datasheet - Page 39

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

0.7
X
X
X
X
X
X
X
X
All other codes
Flash/EE Program Memory Security
The ADuC824 facilitates three modes of Flash/EE program
memory security. These modes can be independently activated,
restricting access to the internal code space. These security
modes can be enabled as part of the user interface available on all
ADuC824 serial or parallel programming tools referenced on the
MicroConverter web page at
The security modes available on the ADuC824 are described
as follows:
Lock Mode
This mode locks code in memory, disabling parallel programming
of the program memory although reading the memory in parallel
mode is still allowed. This mode is deactivated by initiating a
“code-erase” command in serial download or parallel program-
ming modes.
Secure Mode
This mode locks code in memory, disabling parallel programming
(program and verify/read commands) as well as disabling the
execution of a ‘MOVC’ instruction from external memory,
which is attempting to read the op codes from internal memory.
This mode is deactivated by initiating a “code-erase” command
in serial download or parallel programming modes.
Serial Safe Mode
This mode disables serial download capability on the device. If
Serial Safe mode is activated and an attempt is made to reset
the part into serial download mode, i.e., RESET asserted and
deasserted with PSEN low, the part will interpret the serial
download reset as a normal reset only. Therefore, it will not
enter serial download mode but only execute a normal reset
sequence. Serial Safe mode can only be disabled by initiating a
code-erase command in parallel programming mode.
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH) 4-byte pages as shown in
Figure 30.
Table XII. Flash/EE Memory Parallel Programming Modes
0.6
X
X
X
X
X
X
X
X
0.5
X
X
X
X
X
X
X
X
Port 3 Pins
0.4
X
X
1
0
1
0
X
X
0.3
0
0
0
0
0
0
1
1
www.analog.com/microconverter.
0.2
0
0
1
1
1
1
0
0
0.1
0
1
0
0
1
1
0
1
Programming
Mode
Erase Flash/EE
Program, Data, and
Security Modes
Read Device
Signature/ID
Program Code Byte
Program Data Byte
Read Code Byte
Read Data Byte
Program Security
Modes
Read/Verify Security
Modes
Redundant
As with other ADuC824 user-peripheral circuits, the interface to
this memory space is via a group of registers mapped in the SFR
space. A group of four data registers (EDATA1–4) are used to
hold 4-byte page data just accessed. EADRL is used to hold the
8-bit address of the page to be accessed. Finally, ECON is an
8-bit control register that may be written with one of five Flash/EE
memory access commands to trigger various read, write, erase, and
verify functions. These registers can be summarized as follows:
ECON:
EADRL:
EDATA 1–4: SFR Address: BCH to BFH respectively
A block diagram of the SFR interface to the Flash/EE Data
Memory array is shown in Figure 31.
FUNCTION:
RECEIVES COMMAND DATA
FUNCTION:
EADRL
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
9FH
00H
SFR Address: B9H
Function:
Default:
SFR Address: C6H
Function:
Default:
Function:
Default:
9FH
00H
BYTE 1
BYTE 1
BYTE 1 BYTE 2 BYTE 3 BYTE 4
BYTE 1 BYTE 2 BYTE 3 BYTE 4
INTERPRETER LOGIC
BYTE 2
BYTE 2
ECON COMMAND
ECON
Controls access to 640 Bytes
Holds the Flash/EE Data Page
Flash/EE Data Space.
00H
Address. (640 Bytes => 160 Page
Addresses.)
00H
Holds Flash/EE Data memory
page write or page read data bytes.
EDATA1–2 –> 00H
EDATA3–4 –> 00H
BYTE 3
BYTE 3
FUNCTION:
HOLDS THE 4-BYTE
PAGE DATA
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
ADuC824
BYTE 4
BYTE 4
EDATA1 (BYTE 1)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
EDATA2 (BYTE 2)