ADUC824 Analog Devices, ADUC824 Datasheet - Page 48

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

ADuC824
SERIAL PERIPHERAL INTERFACE
The ADuC824 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry standard syn-
chronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full
duplex. It should be noted that the SPI physical interface is shared
with the I
or the other interface at any given time (see SPE in SPICON
below). The system can be configured for Master or Slave operation
and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin), Pin#14
The MISO (master in slave out) pin is configured as an input line
in master mode and an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin#27
The MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin), Pin#26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO data
SPICON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Bits should contain the same values for master and slave devices.
I
S
P
2
Name
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
I
C interface and therefore the user can only enable one
W
Description
SPI Interrupt Bit
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit
Set by user to enable the SPI interface.
Cleared by user to enable the I
SPI Master/Slave Mode Select Bit
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
Clock Polarity Select Bit
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Select Bits
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
SPR1
0
0
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin# 13), can be read via the SPR0 bit.
C
O
L
SPR0
0
1
SPI Control Register
F8H
04H
Yes
S
Selected Bit Rate
f
f
P
CORE
CORE
E
Table XIX. SPICON SFR Bit Designations
/2
/4
2
C interface.
S
P
I
M
SPR1
1
1
lines. A single data bit is transmitted and received in each SCLOCK
period. Therefore, a byte is transmitted/received after eight
SCLOCK periods. The SCLOCK pin is configured as an output
in master mode and as an input in slave mode. In master mode
the bit-rate, polarity and phase of the clock are controlled by
the CPOL, CPHA, SPR0 and SPR1 bits in the SPICON SFR
(see Table XIX). In slave mode the SPICON register will have
to be configured with the phase and polarity (CPHA and CPOL)
of the expected input clock. In both master and slave mode
the data is transmitted on one edge of the SCLOCK signal and
sampled on the other. It is important therefore that the CPHA
and CPOL are configured the same for the master and slave devices.
SS (Slave Select Input Pin), Pin#13
The Slave Select (SS) input pin is only used when the ADuC824
is configured in slave mode to enable the SPI peripheral. This line
is active low. Data is only received or transmitted in slave mode
when the SS pin is low, allowing the ADuC824 to be used in single
master, multislave SPI configurations. If CPHA = 1 then the SS
input may be permanently pulled low. With CPHA = 0 then the
SS input must be driven low before the first bit in a byte wide
transmission or reception and return high again after the last bit
in that byte wide transmission or reception. In SPI Slave Mode,
the logic level on the external SS pin (Pin# 13), can be read
via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
C
P
SPR0
0
1
O
L
Selected Bit Rate
f
f
CORE
CORE
C
/8
/16
P
H
A
S
P
R
1
S
P
R
0