ADAV4622 Analog Devices, ADAV4622 Datasheet - Page 21

• Manufacturer Part Number: ADAV4622
• Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder
• Manufacturer: Analog Devices

Specifications of ADAV4622

• Instructions/cycles: 2560
• Dac Dnr (db): 94dB
• Dac Thd+n: 86dB
• Product Description: Audio Processor for Advanced TV with Sound IF Demodulator and Stereo Decoder

FUNCTIONAL DESCRIPTIONS
SIF PROCESSOR
Supported SIF Standards
The ADAV4622 supports all worldwide standards, as shown in
Table 6.
Table 6. ADAV4622 Worldwide SIF Standards
System
M
N
M
M
BG
BG
I
I
DK1
DK2
DK3
DK
L
L
SIF Demodulation
Figure 22 shows a block diagram of the SIF demodulation
block. The selected SIF input signal is digitized by an ADC with
a sample rate of 24.576 MHz. An AGC is included to ensure
that for even low level signals, the full range of the ADC is used.
The digitized input is passed to the SIF demodulator for
demodulating. The outputs of the demodulator are then passed
to the internal audio processor. Internally, the audio processor
runs at a 48 kHz sampling frequency. When NICAM is selected,
an internal SRC upsamples the 32 kHz NICAM signal to the
audio processor rate of 48 kHz.
Sound
BTSC
BTSC
EIAJ
A2
A2
NICAM
Mono
NICAM
A2
A2
A2
NICAM
Mono
NICAM
4.5MHz ~ 6.742MHz
SIF INPUT
SC1 (MHz)
4.5
4.5
4.5
4.5
5.5
5.5
6.0
6.0
6.5
6.5
6.5
6.5
6.5
6.5
SIF_IN1
SIF_IN2
SC2 (MHz)
–
–
–
4.724
5.742
5.85
6.552
6.258
6.742
5.742
5.85
5.85
–
–
AGC
Figure 22. SIF Demodulation
Rev. B | Page 21 of 28
24.576MHz
ADC
SIF Processor Configuration
The ADAV4622 supports automatic standard detection, which
is enabled by default. The ASD controller configures the SIF
processor with the optimum register settings based on the
detected standard. If the user prefers to operate in manual mode,
or if the user prefers to use an external ASD loop, all of the ASD
status registers are available.
MASTER CLOCK OSCILLATOR
Internally, the ADAV4622 operates synchronously to the master
MCLKI input. All internal system clocks are generated from
this single clock input using an internal PLL. This MCLKI input
can also be generated by an external crystal oscillator connected
to the MCLKI/XIN pin or by using a simple crystal resonator
connected across MCLKI/XIN and XOUT. By default, the
master clock frequency is 24.576 MHz; however, by using the
internal dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and
3.072 MHz are also supported.
EXTERNAL CLOCK/
SC1
SC2
CRYSTAL
FM/DQPSK/AM
PARAMETERS
DEMOD
I
2
ASD
SIF
C
Figure 21. Master Clock
A
B
REGISTER
DIVIDER
OSC
DIVIDER WORD
[÷8, ÷4, ÷2, ÷1]
MASTER CLOCK FREQUENCY
[24.576MHz, 12.288MHz,
6.144MHz, 3.072MHz]
3.072MHz
ADAV4622
PLL
REFERENCE
CLOCK