TDA7333013TR STMicroelectronics, TDA7333013TR Datasheet - Page 13

• Manufacturer Part Number: TDA7333013TR
• Description: IC PROCESSOR RDS/RBDS 16-TSSOP
• Manufacturer: STMicroelectronics
• Type: RDS/RBDS Signal Processorr

Specifications of TDA7333013TR

• Applications: Radio
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA7333
3.5
Demodulator
The demodulator includes:
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●
●
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Figure 7.
The demodulator is fed by the 57 kHz bandpass filter and interpolated multiplex signal. The
input signal passes a digital filter extracting the sinus and cosinus components, to be used
for further processing.
The sign of both channels are used as input for the ARI indicator and for the 57 kHz PLL.
A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present,
the 57 kHz PLL is operating as a normal PLL, else it is operating as a Costas loop.
One part of the PLL is compensating the integral offset (frequency deviation between
oscillator and input signal).
One channel of the filter is fed into the half wave integrator. Two half waves are created, with
a phase deviation of 90 degrees. One wave represents the RDS component, whereas the
other wave represents the ARI component. The sign of both waves are used as reference
for the bit PLL (1187.5 Hz).
The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which
after integration and differential decoding represents the RDS data.
In a similar way a quality bit can be calculated. This is useful to optimize error correction.
The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 MHz clock may be used
by setting the corresponding bit in rds_bd_ctrl register (see
In order to optimize the error correction in the group and block synchronization module, the
sensitivity level of the quality bit can be adjusted in three steps (see
RDS quality indicator with selectable sensitivity
Selectable time constant of 57 kHz PLL
Selectable time constant of bit PLL
time constant selection done automatically or by software
from RDS group and block synchronisation
to RDS group and block synchronisation
(8,550 or 8,664 MHz)
Demodulator block diagram
module:
RD
RDSDAT
RDSQUAL
AR_RES
mclk
MPX
module:
(digital Filter)
Input-stage
Half Wave
Integrator
Cosine comp.
Sine comp.
ARI-indicator
mclk
1187.5Hz
PLL
Half Wave
Extractor
57 kHz PLL
Clock Generator
Chapter
Functional description
Chapter
3.7.6).
RDS Data
Extractor
RDS Quality
Extractor
frequency
offset comp.
3.7.6). Only
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