LPC1112FDH28 NXP Semiconductors, LPC1112FDH28 Datasheet - Page 49

• Manufacturer Part Number: LPC1112FDH28
• Description: The LPC1112FDH28 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC111X
Product data sheet
7.16.5.2 Sleep mode
7.16.5.3 Deep-sleep mode
7.16.5.4 Deep power-down mode
7.17.1 Start logic
7.17 System control
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC1110/11/12/13/14/15 can wake up from Deep power-down mode
via the WAKEUP pin.
A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in
NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when
the chip is running. In addition, an input signal on the start logic pins can wake up the chip
from Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
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Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
Table 9
All information provided in this document is subject to legal disclaimers.
to
Table 10
Rev. 7 — 1 March 2012
as input to the start logic has an individual interrupt in the
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2012. All rights reserved.
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