LPC12D27FBD100 NXP Semiconductors, LPC12D27FBD100 Datasheet - Page 36

• Manufacturer Part Number: LPC12D27FBD100
• Description: The LPC12D27FBD100 is a ARM Cortex-M0 based microcontroller for embedded applications featuring a high level of integration and low power consumption
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 16.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
LPC12D27
Product data sheet
Symbol
f
t
t
t
t
t
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
Parameters are valid over operating temperature range unless otherwise specified.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
bridge the undefined region of the falling edge of SCL.
C
The maximum t
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
The maximum t
t
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
A Fast-mode I
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
=
b

= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
40
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t

Dynamic characteristics: I
C to +85
11.5 I
2
C-bus device can be used in a Standard-mode I
Parameter
SCL clock
frequency
fall time
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up time
f
HD;DAT
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

C.
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
[1]
2
C-bus
[2][3][4][5]
[6][2][7]
[8][9]
2
C-bus pins
All information provided in this document is subject to legal disclaimers.
f
.
Rev. 1 — 20 September 2011
Conditions
Standard-mode 0
Fast-mode
Fast-mode Plus 0
of both SDA
and SCL
signals
Standard-mode 4.7
Fast-mode
Fast-mode Plus 0.5
Standard-mode 4.0
Fast-mode
Fast-mode Plus 0.26
Standard-mode 0
Fast-mode
Fast-mode Plus 0
Standard-mode 250
Fast-mode
Fast-mode Plus 50
Standard-mo
de
Fast-mode
Fast-mode
Plus
2
C-bus system but the requirement t
Min
0
-
20 + 0.1  C
-
1.3
0.6
0
100
r(max)
+ t
32-bit ARM Cortex-M0 microcontroller
SU;DAT
b
= 1000 + 250 = 1250 ns (according to the
Max
100
400
1
300
300
120
-
-
-
-
-
-
-
-
-
-
-
-
SU;DAT
IH
(min) of the SCL signal) to
= 250 ns must then be met.
LPC12D27
LOW
© NXP B.V. 2011. All rights reserved.
) of the SCL signal. If
Unit
kHz
kHz
MHz
ns
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
f
is specified at
VD;DAT
36 of 46
or