LPC1788FBD144 NXP Semiconductors, LPC1788FBD144 Datasheet - Page 42

• Manufacturer Part Number: LPC1788FBD144
• Description: The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
LPC178X_7X
Objective data sheet
Address range
0x0000 0000 to
0x1FFF FFFF
0x2000 0000 to
0x3FFF FFFF
0x4000 0000 to
0x7FFF FFFF
0x8000 0000 to
0xDFFF FFFF
0xE000 0000 to
0xE00F FFFF
LPC178x/177x memory usage and details
7.7 Memory map
General Use
On-chip non-volatile
memory
On-chip SRAM
Boot ROM
On-chip SRAM
(typically used for
peripheral data)
AHB peripherals
APB Peripherals
Off-chip Memory via
the External Memory
Controller
Cortex-M3 Private
Peripheral Bus
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
The LPC178x/7x incorporate several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
Figure 6
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Address range details and description
0x0000 0000 - 0x0007 FFFF
0x0000 0000 - 0x0003 FFFF
0x0000 0000 - 0x0001 FFFF
0x0000 0000 - 0x0000 FFFF
0x1000 0000 - 0x1000 FFFF
0x1000 0000 - 0x1000 7FFF
0x1000 0000 - 0x1000 3FFF
0x1FFF 0000 - 0x1FFF 1FFF
0x2000 0000 - 0x2000 1FFF
0x2000 2000 - 0x2000 3FFF
0x2000 4000 - 0x2000 7FFF
0x2008 0000 - 0x200B FFFF
0x4000 0000 - 0x4007 FFFF
0x4008 0000 - 0x400F FFFF
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF
0x9000 0000 - 0x93FF FFFF
0x9800 0000 - 0x9BFF FFFF
0x9C00 0000 - 0x9FFF FFFF
Four dynamic memory chip selects:
0xA000 0000 - 0xAFFF FFFF
0xB000 0000 - 0xBFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xD000 0000 - 0xDFFF FFFF
0xE000 0000 - 0xE00F FFFF
shows the overall map of the entire address space from the user
Rev. 3 — 27 December 2011
For devices with 512 kB of flash memory.
For devices with 256 kB of flash memory.
For devices with 128 kB of flash memory.
For devices with 64 kB of flash memory.
For devices with 64 kB of local SRAM.
For devices with 32 kB of local SRAM.
For devices with 16 kB of local SRAM.
8 kB Boot ROM with flash services.
Peripheral RAM - bank 0 (first 8 kB)
Peripheral RAM - bank 0 (second 8 kB)
Peripheral RAM - bank 1 (16 kB)
See
APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
Static memory chip select 0 (up to 64 MB)
Static memory chip select 1 (up to 64 MB)
Static memory chip select 2 (up to 64 MB)
Static memory chip select 3 (up to 64 MB)
Dynamic memory chip select 0 (up to 256MB)
Dynamic memory chip select 1 (up to 256MB)
Dynamic memory chip select 2 (up to 256MB)
Dynamic memory chip select 3 (up to 256MB)
Cortex-M3 related functions, includes the NVIC
and System Tick Timer.
32-bit ARM Cortex-M3 microcontroller
Figure 6
for details
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
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