LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 2

• Manufacturer Part Number: LPC1820FET100
• Description: The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
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Configurable digital peripherals:
Serial interfaces:
Digital peripherals:
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Ultra-low power RTC crystal oscillator.
Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
Clock output.
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like timers, SCT, and ADC0/1.
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 40 MB
per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY. USB interface
electrical test software included in ROM USB stack.
Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support synchronous mode and a smart
card interface conforming to ISO7816 specification.
Two C_CAN 2.0B controllers with one channel each.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One Fast-mode Plus I
pins conforming to the full I
1 Mbit/s.
One standard I
Two I
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
LCD controller with DMA support and a programmable display resolution of up to
1024 H  768 V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
SD/MMC card interface.
Eight-channel General-Purpose DMA (GPDMA) controller can access all memories
on the AHB and all DMA-capable AHB slaves.
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain modes.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to 8 GPIO pins can be selected from all GPIO pins as edge and level sensitive
interrupt sources.
2
S interfaces with DMA support, each with one input and one output.
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 15 December 2011
2
C-bus interface with monitor mode and standard I/O pins.
2
C-bus interface with monitor mode and with open-drain I/O
2
C-bus specification. Supports data rates of up to
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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