JN5148 NXP Semiconductors, JN5148 Datasheet - Page 23

• Manufacturer Part Number: JN5148
• Description: The JN5148 is an ultra low power, high performance MCU combined with an IEEE802
• Manufacturer: NXP Semiconductors

6.4 Brown-out Detect
An internal brown-out detect module is used to monitor the supply voltage to the JN5148; this can be used whilst the
device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and
can be used to cause the JN5148 to perform a chip reset. Equally, dips in the supply voltage can be detected and
used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it.
The brown-out detect is enabled by default from power-up and can extend the reset during power-up. This will keep
the CPU in reset until the voltage exceeds the brown-out threshold voltage. The threshold voltage is configurable to
2.0V, 2.3V, 2.7V and 3.0V and is controllable by software. From power-up the threshold is set by eFuse settings and
the default chip configuration is for the 2.3V threshold. It is recommended that the threshold is set so that, as a
minimum, the chip is held in reset until the voltage reaches the level required by the external memory device on the
SPI interface.
6.5 Watchdog Timer
A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the 32kHz system
clock. A pre-scaler is provided to allow the expiry period to be set between typically 8ms and 16.4 seconds. Failure
to restart the watchdog timer within the pre-configured timer period will cause a chip reset to be performed. A status
bit is set if the watchdog was triggered so that the software can differentiate watchdog initiated resets from other
resets, and can perform any required recovery once it restarts. If the source of the 32kHz system clock is the 32kHz
RC oscillator then the watchdog expiry periods are subject to the variation in period of the RC oscillator.
After power up, reset, start from deep sleep or start from sleep, the watchdog is always enabled with the largest
timeout period and will commence counting as if it had just been restarted. Under software control the watchdog can
be disabled. If it is enabled, the user must regularly restart the watchdog timer to stop it from expiring and causing a
reset. The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or
deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if
enabled once the debugger un-stalls the CPU.
© NXP Laboratories UK 2011
JN-DS-JN5148-001 1v7
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