BUK9MRR-65PKK NXP Semiconductors, BUK9MRR-65PKK Datasheet
BUK9MRR-65PKK
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BUK9MRR-65PKK Summary of contents
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... BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET Rev. 02 — 17 June 2010 1. Product profile 1.1 General description Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes ...
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... Graphic symbol SOT163-1 (SO20) Description plastic small outline package; 20 leads; body width 7.5 mm All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET FET1 FET2 G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2 ...
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... HBM 100 pF 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET Min Typ Max - - ...
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... Single-Pulse and repetitive avalanche rating; avalanche current as a function of avalanche time. FET1 and FET2. Limit DSon All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET (1) (2) (3) −3 −2 − 001aal761 = 10 μ ...
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... Figure 5 mounted on a printed-circuit board; one channel conducting; 400 mm² copper heat sink area; see Figure 7; see Figure 5 All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET Min Typ Max - - ...
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... Fig 7. PCB used for thermal tests; heat sink area 400 mm² All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET 003aac472 (1) (2) 100 200 300 ...
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... Transient thermal impedance from junction to ambient as a function of pulse duration BUK9MRR-65PKK Product data sheet −5 −4 −3 −2 − All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET 001aal808 t p δ ...
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... Ω R G(ext Ω Ω R G(ext) from pin to center of die All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET Min Typ Max 1 ...
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... A/µ - 001aal787 (V) GS Fig 10. Forward transconductance as a function of All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET Min Typ - 2 - 0.85 - 41.4 - 0.087 ...
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... GS Fig 12. Output characteristics: drain current as a 001aam030 V GS(th) max (V) GS Fig 14. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET ( function of drain-source voltage ...
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... V (V) GS Fig 18. Temperature sense diode forward voltage as a function of junction temperature; typical values, FET1 and FET2 All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET 003aae513 2.0 2.5 3.5 4.0 4.5 V (V) = ...
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... Fig 20. Input, output and reverse transfer capacitances ( 0.5 1 All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET (pF function of drain-source voltage; typical ...
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... REFERENCES JEDEC JEITA MS-013 All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET θ detail ...
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... NXP Semiconductors 8. Revision history Table 7. Revision history Document ID Release date BUK9MRR-65PKK v.2 20100617 • Modifications: Status changed from objective to product. BUK9MRR-65PKK v.1 20100528 BUK9MRR-65PKK Product data sheet Data sheet status Change notice Product data sheet - Objective data sheet - All information provided in this document is subject to legal disclaimers. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET © NXP B.V. 2010. All rights reserved ...
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... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 17 June 2010 BUK9MRR-65PKK Dual TrenchPLUS FET Logic Level FET © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: BUK9MRR-65PKK All rights reserved. Date of release: 17 June 2010 ...