STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 130

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

General-purpose timers
10.1.5
Note:
130/232
Input capture mode
In input capture mode, a capture/compare register (TIMx_CCRy) latches the value of the
counter after a transition is detected by the corresponding ICy signal. When a capture
occurs, the corresponding INT_TIMCCyIF flag in the INT_TIMxFLAG register is set, and an
interrupt request is sent if enabled.
If a capture occurs when the INT_TIMCCyIF flag is already high, then the missed capture
flag INT_TIMMISSCCyIF in the INT_TIMxMISS register is set. INT_TIMCCyIF can be
cleared by software writing a 1 to its bit or reading the captured data stored in the
TIMx_CCRy register. To clear the INT_TIMMISSCCyIF bit, write a 1 to it.
The following example shows how to capture the counter value in the TIMx_CCR1 when the
TI1 input rises.
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To detect missed captures reliably, read captured data in TIMxCCRy before checking the
missed capture/compare flag. This sequence avoids missing a capture that could happen
after reading the flag and before reading the data.
Software can generate IC interrupt requests by setting the corresponding TIM_CCyG bit in
the TIMx_EGR register.
Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the
TIM_CC1S bits to 01 in the TIMx_CCMR1 register. As soon as TIM_CC1S becomes
different from 00, the channel is configured in input and the TIMx_CCR1 register
becomes read-only.
Program the required input filter duration with respect to the signal connected to the
timer, when the input is one of the TIy (ICyF bits in the TIMx_CCMR1 register).
Consider a situation in which, when toggling, the input signal is unstable during at most
5 internal clock cycles. The filter duration must be longer than these 5 clock cycles. The
transition on TI1 can be validated when 8 consecutive samples with the new level have
been detected (sampled at PCLK frequency). To do this, write the TIM_IC1F bits to
0011 in the TIMx_CCMR1 register.
Select the edge of the active transition on the TI1 channel by writing the TIM_CC1P bit
to 0 in the TIMx_CCER register (rising edge in this case).
Program the input prescaler: In this example, the capture is to be performed at each
valid transition, so the prescaler is disabled (write the TIM_IC1PS bits to 00 in the
TIMx_CCMR1 register).
Enable capture from the counter into the capture register by setting the TIM_CC1E bit
in the TIMx_CCER register.
If needed, enable the related interrupt request by setting the INT_TIMCC1IF bit in the
INT_TIMxCFG register.
When an input capture occurs:
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The TIMx_CCR1 register gets the value of the counter on the active transition.
INT_TIMCC1IF flag is set (capture/compare interrupt flag). The missed
capture/compare flag INT_TIMMISSCC1IF in INT_TIMxMISS is also set if another
capture occurs before the INT_TIMCC1IF flag is cleared.
An interrupt may be generated if enabled by the INT_TIMCC1IF bit.
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Doc ID 16252 Rev 13