STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 49
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STM32W108CZ
Manufacturer Part Number
STM32W108CZ
Description
High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
Manufacturer
STMicroelectronics
Datasheet
1.STM32W108CC.pdf
(232 pages)
Specifications of STM32W108CZ
Receive Current (w/ Cpu)
27 mA
Transmit Current (w/ Cpu, +3 Dbm Tx)
31 mA
Low Deep Sleep Current, With Retained Ram And Gpio
400 nA/800 nA with/without sleep timer
Standard Arm Debug Capabilities
Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
Single Voltage Operation
2.1-3.6 V with internal 1.8 V and 1.25 V regulators
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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 15.
Table 16.
31
15
31
15
30
14
30
14
Bits [15:0]
Bits [15:0]
Sleep timer compare A low register (SLEEPTMR_CMPAL)
Address:
Reset value:
Sleep timer compare A low register (SLEEPTMR_CMPAL)
Sleep timer compare B high register (SLEEPTMR_CMPBH)
Address:
Reset value:
Sleep timer compare B high register (SLEEPTMR_CMPBH)
29
13
29
13
SLEEPTMR_CMPAL_FIELD:
SLEEPTMR_CMPBH_FIELD:
Sleep timer compare A low value [15:0].
Writing to this register puts value in hold register until a write to the SLEEPTMR_CMPAH
register.
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.
Therefore it is recommended to disable interrupts before changing this register.
Sleep timer compare B high value [31:16].
Sleep timer compare value, writing updates COMP_B_H (directly) and COMP_B_L (from
hold register).
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.
Therefore it is recommended to disable interrupts before changing this register.
28
12
28
12
27
11
27
11
0x4000 601C
0x0000 FFFF
0x4000 6020
0x0000 FFFF
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 13
SLEEPTMR_CMPBH
SLEEPTMR_CMPAL
24
24
8
8
Reserved
Reserved
rw
rw
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
System modules
18
18
2
2
17
17
1
1
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16
0
0
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