STM8S903K3 STMicroelectronics, STM8S903K3 Datasheet - Page 26

• Manufacturer Part Number: STM8S903K3
• Description: 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640 bytes EEPROM
• Manufacturer: STMicroelectronics

Specifications of STM8S903K3

• Program Memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
• Data Memory: 640 bytes true data EEPROM; endurance 300 kcycles
• Ram: 1 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

Pinout and pin description
26/115
SDIP
32
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
(1)
"Absolute maximum ratings").
(2)
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V DD are not implemented)
UFQFPN/
LQFP32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
PB6
PB5/ I2C_SDA [TIM1_BKIN]
PB4/ I2C_SCL [ADC_ETR]
PB3/ AIN3/TIM1_ETR
PB2/ AIN2/ TIM1_CH3N
PB1/ AIN1/ TIM1_CH2N
PB0/ AIN0/ TIM1_CH1N
PE5/ SPI_NSS [TIM1_CH1N]
PC1/ TIM1_CH1/ UART1_CK
[TIM1_CH2N]
PC2/ TIM1_CH2 [TIM1_CH3N]
PC3/ TIM1_CH3/TLI/[TIM1_CH1N
]
PC4/ TIM1_CH4/
CLK_CCO/AIN2/[TIM1_CH2N]
PC5/SPI_SCK [TIM5_CH1]
PC6/ SPI_MOSI [TIM1_CH1]
PC7/ SPI_MISO [TIM1_CH2]
PD0/ TIM1_BKIN [CLK_CCO]
PD1/ SWIM
PD2/AIN3/ [TIM5_CH3]
PD3/ AIN4/ TIM5_CH2/ ADC_ETR
PD4/ TIM5_CH1/ BEEP
[UART1_CK]
PD5/ AIN5/ UART1_TX
PD6/ AIN6/ UART1_RX
PD7/ TLI [TIM1_CH4]
(4)
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
floating
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
wpu
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ext.
interrupt
DocID15590 Rev 6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Output
High
sink
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
(1)
Speed
O1
O1
O1
O3
O3
O3
O3
O3
O3
O3
O3
O3
O3
O3
O3
O3
O4
O3
O3
O3
O3
O3
O3
OD
X
T
T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(3)
(3)
PP
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Main
function
(after
reset)
Port
B6
Port
B5
Port
B4
Port
B3
Port
B2
Port
B1
Port
B0
Port
E5
Port
C1
Port
C2
Port
C3
Port
C4
Port
C5
Port
C6
Port
C7
Port
D0
Port
D1
Port
D2
Port
D3
Port
D4
Port
D5
Port
D6
Port
D7
Default alternate function
I
I
Analog input 3/ Timer 1
external trigger
Analog input 2/ Timer 1 -
inverted channel 3
Analog input 1/ Timer 1 -
inverted channel 2
Analog input 0/ Timer 1 -
inverted channel 1
SPI master/ slave select
Timer 1 - channel 1
UART1 clock
Timer 1 - channel 2
Timer 1 - channel 3
Timer 1 - channel 4
/configurable clock output
SPI clock
PI master out/slave in
SPI master in/ slave out
Timer 1 - break input
SWIM data interface
Analog input 4 Timer 52 -
channel 2/ADC external
trigger
Timer 5 - channel 1/BEEP
output
Analog input 5/ UART1
data transmit
Analog input 6/ UART1
data receive
Top level interrupt
2
2
C data
C clock
STM8S903K3 STM8S903F3
Alternate function after remap
[option bit]
Timer 1 - break input [AFR4]
ADC external trigger [AFR4]
Timer 1 - inverted channel 1
[AFR1:0]
Timer 1 - inverted channel 2
[AFR1:0]
Timer 1 - inverted channel 3
[AFR1:0]
Top level interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]
Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]
Timer 5 channel 1 [AFR0]
Timer 1 channel 1 [AFR0]
Timer 1 channel 2[AFR0]
Configurable clock output
[AFR5]
Analog input 3 [AFR2] Timer 52
- channel 3 [AFR1]
UART clock [AFR2]
Timer 1 - channel 4 [AFR6]