ST72324LK2 STMicroelectronics, ST72324LK2 Datasheet - Page 74
ST72324LK2
Manufacturer Part Number
ST72324LK2
Description
3V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324LK2.pdf
(154 pages)
Specifications of ST72324LK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
16-bit Timer A With
1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
16-bit Timer B With
2 input captures, 2 output compares, PWM and pulse generator modes
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ST72324Lxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 44. Single Master/ Single Slave Application
74/154
1
44.
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
LSBit
SCK
MOSI
SS
MISO
+5V
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MISO
MOSI
SCK
SS
Figure
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
47) but master and slave
SLAVE
LSBit
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