ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 180

• Manufacturer Part Number: ST72521R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72521R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

Controller area network (CAN)
Note:
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Resync
The resynchronization mode is used to find the correct entry point for starting transmission
or reception after the node has gone asynchronous either by going into the Standby or bus-
off states.
Resynchronization is achieved when 128 sequences of 11 recessive bits have been
monitored unless the node is not bus-off and the FSYN bit in the CSR register is set in which
case a single sequence of 11 recessive bits needs to be monitored.
Idle
The CAN controller looks for one of the following events: The RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7 register of the currently active page is written
to.
Transmission
Once the LOCK bit of a Buffer Control/Status Register (BCSRx) has been set and read back
as such, a transmit job can be submitted by writing to the DATA7 register. The message with
the highest priority will be transmitted as soon as the CAN bus becomes idle. Among those
messages with a pending transmission request, the highest priority is given to Buffer 3, then
2 and 1. If the transmission fails due to a lost arbitration or to an error while the NRTX bit of
the CSR register is reset, then a new transmission attempt is performed. This goes on until
the transmission ends successfully or until the job is cancelled by unlocking the buffer, by
setting the NRTX bit or if the node ever enters bus-off or if a higher priority message
becomes pending. The RDY bit in the BCSRx register, which was set since the job was
submitted, gets reset. When a transmission is in progress, the BUSY bit in the BCSRx
register is set. If it ends successfully then the TXIF bit in the Interrupt Status Register (ISR)
is set, otherwise the TEIF bit is set. An interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
Setting the SRTE bit of the CSR register allows transmitted messages to be simultaneously
received when they pass the acceptance filtering. This is particularly useful for checking the
integrity of the communication path.
Reception
Once the CAN controller has synchronized itself onto the bus activity, it is ready for
reception of new messages. The identifier of every incoming message is compared to the
acceptance filters. If the bitwise comparison of the selected bits ends up with a match for at
least one of the filters then that message is elected for reception and a target buffer is
searched for. This buffer will be the first one - order is 1 to 3 - that has the LOCK and RDY
bits of its BCSRx register reset.
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Up to three messages can be automatically received without intervention from the CPU
because each buffer has its own set of status bits, greatly reducing the reactiveness
requirements in the processing of the receive interrupts.
When no such buffer exists then an overrun interrupt is generated if the ORIE bit of the
ICR register has been set. In this case the identifier of the last message is made
available in the Last Identifier Register (LIDHR and LIDLR) at least until it is overwritten
by a new identifier picked-up from the bus.
When a buffer does exist, the accepted message gets written into it, the ACC bit in the
BCSRx register gets the number of the matching filter, the RDY and RXIF bits get set
and an interrupt is generated if the RXIE bit in the ISR register is set.
Doc ID 17660 Rev 1
ST72521xx-Auto