ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 183

• Manufacturer Part Number: ST72521R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72521R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72521xx-Auto
Caution:
Table 91.
Interrupt flags are reset by writing a ‘0’ to the corresponding bit position. The appropriate
way consists in writing an immediate mask or the one’s complement of the register content
initially read by the interrupt handler. Bit manipulation instruction BRES should never be
used due to its read-modify-write nature.
Bit Name
6
5
4
3
2
1
0
RXIF2
RXIF1
EPND
ORIF
SCIF
TXIF
TEIF
Receive Interrupt Flag for Buffer 2
Receive Interrupt Flag for Buffer 1
Transmit Interrupt Flag
Status Change Interrupt Flag
Overrun Interrupt Flag
Transmit Error Interrupt Flag
Error Interrupt Pending
ISR register description (continued)
Set by hardware to signal that a new error-free message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Set by hardware to signal that a new error-free message is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
Set by hardware to signal that the highest priority message queued for transmission
has been successfully transmitted.
Cleared by software.
Set by hardware to signal the reception of a dominant bit while in standby mode. In
Run mode this bit is set when EPVS is set or reset (refer to
diagram). This bit also signals any receive error when ESCI = 1.
Cleared by software.
Set by hardware to signal that a message could not be stored because no receive
buffer was available.
Cleared by software.
Set by hardware to signal that an error occurred during the transmission of the highest
priority message queued for transmission.
Cleared by software.
Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or
TEIF is set.
Reset by hardware when all error interrupt flags have been cleared.
Doc ID 17660 Rev 1
Function
Controller area network (CAN)
Figure 73: CAN error state
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