ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 181

• Manufacturer Part Number: ST72521R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72521R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72521xx-Auto
17.3.4
Error
The error management as described in the CAN protocol is completely handled by hardware
using two error counters which are incremented or decremented according to the error
condition. Both of them may be read by the application to determine the stability of the
network. Moreover, as one of the node status bits (EPSV or BOFF of the CSR register)
changes, an interrupt is generated if the SCIE bit is set in the ICR Register. Refer to
Figure
Figure 73. CAN error state diagram
Bit timing logic
The bit timing logic monitors the serial bus-line and performs sampling and adjustment of
the sample point by synchronizing on the start-bit edge and resynchronizing on following
edges.
Explaining its operation is simplified when the nominal bit time is divided into segments as
follows:
●
●
●
●
When 128 * 11 recessive bits occur:
- the BOFF bit is cleared
- the TECR register is cleared
- the RECR register is cleared
Synchronization segment (SYNC_SEG): A bit change is expected to lie within this
time segment. It has a fixed length of one time quanta (1 x t
Bit segment 1 (BS1): Defines the location of the sample point. It includes the
PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable
between 1 and 16 time quanta but may be automatically lengthened to compensate for
positive phase drifts due to differences in the frequency of the various nodes of the
network.
Bit segment 2 (BS2): Defines the location of the transmit point. It represents the
PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8
time quanta but may also be automatically shortened to compensate for negative
phase drifts.
Resynchronization Jump Width (RJW): Defines an upper boundary to the amount of
lengthening or shortening of the bit segments. It is programmable between 1 and 4 time
quanta.
73.
ERROR ACTIVE
When TECR or RECR > 127, the EPSV bit is set
Doc ID 17660 Rev 1
When TECR and RECR < 128,
the EPSV bit is cleared
BUS OFF
Controller area network (CAN)
ERROR PASSIVE
When TECR > 255, the BOFF bit is set
and the EPSV bit is cleared
CAN
).
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