ST92250CV2Q-Auto STMicroelectronics, ST92250CV2Q-Auto Datasheet - Page 181
ST92250CV2Q-Auto
Manufacturer Part Number
ST92250CV2Q-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet
1.ST92150JDV1QAUTO.pdf
(430 pages)
Specifications of ST92250CV2Q-Auto
Internal Memory
Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
Minimum Instruction Time
83 ns (24 MHz int. clock)
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EXTENDED FUNCTION TIMER (Cont’d)
10.3.5 Register Description
Each Timer is associated with three control and
one status registers, and with six pairs of data reg-
isters (16-bit values) relating to the two input cap-
tures, the two output compares, the counter and
the alternate counter.
Notes:
1. In the register description on the following pag-
es, register and page numbers are given using the
example of Timer 0. On devices with more than
one timer, refer to the device register map for the
adresses and page numbers.
2. To work correctly with register pairs, it is strong-
ly recommended to use single byte instructions.
Do not use word instructions to access any of the
16-bit registers.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
R240 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
MSB
7
LSB
0
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
R241 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
R242 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
R243 - Read Only
Register Page: 28
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
MSB
MSB
MSB
7
7
7
181/430
LSB
LSB
LSB
0
0
0
9
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