ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 111

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

INTERRUPT REGISTERS (Cont’d)
INTERRUPT PRIORITY LEVEL REGISTER LOW
(SIPLRL)
R253 - Read/Write
Register Page: Page 60
Reset Value : 1111 1111
Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level.
Bits 5:4 = PL2G, PL1G: INTG0, G1 Priority Level.
Bits 3:2 = PL2F, PL1F: INTF0, F1 Priority Level.
Bits 1:0 = PL2E, PL1E: INTE0, E1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
Table 22. PL Bit Assignment
Table 23. PL bit Meaning
PL2H
Interrupt Channel
7
PL2x
0
0
1
1
INTG0
INTG1
INTH0
INTH1
INTF0
INTF1
INTE0
INTE1
PL1H
Pair
PL1x
PL2G
0
1
0
1
PL1G
Hardware bit
PL2G
PL2G
PL2H
PL2H
PL2E
PL2E
PL2F
PL2F
3-bit Priority Level
PL2F
0
1
0
1
0
1
0
1
PL1G
PL1G
PL1H
PL1H
PL1E
PL1E
PL1F
PL1F
PL1F
0 (Highest)
1
2
3
4
5
6
7 (Lowest)
PL2E
Priority
0
1
0
1
0
1
0
1
PL1E
0
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
INTERRUPT FLAG REGISTER HIGH
(SFLAGRH)
R254 - Read Only
Register Page: 60
Reset Value : 0000 0000
Bit 0 = OUFI0 : Overrun flag for INTI0
This bit is set and cleared by hardware. It indicates
if more than one interrupt event occured on INTI0
before the IPI0 bit in the SIPRH register has been
cleared.
0 : No overrun
1 : Overrun has occurred on INTI0
INTERRUPT FLAG REGISTER LOW
(SFLAGRL)
R255 - Read Only
Register Page: 60
Reset Value : 0000 0000
Bits 7:0 = OUFxx : Overrun flag for channel xx
These bits are set and cleared by hardware. They
indicate if more than one interrupt event occurs on
the associated channel before the pending bit in
the SIPRL register has been cleared.
0 : No overrun
1 : Overrun has occurred on channel xx
OUFH1 OUFH0
Interrupt Channel
7
7
-
INTG0
INTG1
INTE0
INTE1
INTH0
INTH1
INTF0
INTF1
Pair
-
OUFG1
-
OUFG0 OUFF1
PL2G
PL2G
PL2E
PL2E
PL2H
PL2H
PL2F
PL2F
-
Priority Level
-
PL1G
PL1G
PL1H
PL1H
PL1E
PL1E
PL1F
PL1F
OUFF0
-
OUFE1
-
0
1
0
1
0
1
0
1
111/430
OUFE0
OUFI0
0
0
9