ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 266

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
I
Next, depending on the data direction bit (least
significant bit of the address byte), and after the
generation of an acknowledge, the slave must go
in sending or receiving mode.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1).
Slave Receiver
Following the address reception and after I2CSR1
register has been read, the slave receives bytes
from the SDA line into the Shift Register and sends
them to the I2CDR register. After each byte it
generates an acknowledge bit if the I2CCR.ACK
bit is set.
When
I2CSR1.BTF flag is set and an interrupt is generat-
ed if the I2CCR.ITE bit is set (see
Transfer sequencing EV2).
Then the interface waits for a read of the I2CSR1
register followed by a read of the I2CDR register,
or waits for the DMA to complete.
Slave Transmitter
Following the address reception and after I2CSR1
register has been read, the slave sends bytes from
the I2CDR register to the SDA line via the internal
shift register.
When the acknowledge bit is received, the
I2CCR.BTF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see
128
The slave waits for a read of the I2CSR1 register
followed by a write in the I2CDR register or waits
for the DMA to complete, both holding the SCL
line low (except on EV3-1).
Error Cases
– BERR: Detection of a Stop or a Start condition
266/430
9
2
C BUS INTERFACE (Cont’d)
during a byte transfer.
The I2CSR2.BERR flag is set and an interrupt is
generated if I2CCR.ITE bit is set.
If it is a stop then the state machine is reset.
If it is a start then the state machine is reset and
it waits for the new slave address on the bus.
Transfer sequencing EV3).
the
acknowledge
bit
is
Figure 128
sent,
Figure
the
– AF: Detection of a no-acknowledge bit.
Note: In both cases, SCL line is not stretched low;
however, the SDA line, due to possible «0» bits
transmitted last, can remain low. It is then neces-
sary to release both lines by software.
Other Events
– ADSL: Detection of a Start condition after an ac-
– STOPF: Detection of a Stop condition after an
How to release the SDA / SCL lines
Check that the I2CSR1.BUSY bit is reset. Set and
subsequently clear the I2CCR.STOP bit while the
I2CSR1.BTF bit is set; then the SDA/SCL lines are
released immediately after the transfer of the cur-
rent byte.
This will also reset the state machine; any subse-
quent STOP bit (EV4) will not be detected.
10.8.4.2 I
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Setting
I2CSR1.BUSY bit is cleared causes the interface
to generate a Start condition.
Once the Start condition is generated, the periph-
eral is in master mode (I2CSR1.M/SL=1) and
I2CSR1.SB (Start bit) flag is set and an interrupt is
generated if the I2CCR.ITE bit is set (see
128
The interface waits for a read of the I2CSR1 regis-
ter followed by a write in the I2CDR register with
the Slave address, holding the SCL line low.
The I2CSR2.AF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set.
knowledge time-slot.
The state machine is reset and starts a new proc-
ess. The I2CSR1.ADSL flag bit is set and an in-
terrupt is generated if the I2CCR.ITE bit is set.
The SCL line is stretched low.
acknowledge time-slot.
The state machine is reset. Then the
I2CSR2.STOPF flag is set and an interrupt is
generated if the I2CCR.ITE bit is set.
Transfer sequencing EV5 event).
2
the
C Master Mode
I2CCR.START
bit
while
Figure
the