ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 160

no-image

ST92124V1Q-Auto

Manufacturer Part Number
ST92124V1Q-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92124V1Q-Auto

Internal Memory
Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
Minimum Instruction Time
83 ns (24 MHz int. clock)
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
TIMER/WATCHDOG (Cont’d)
10.1.3.3 Preventing Watchdog System Reset
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting re-
starts from the preset value.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
Figure 88. Watchdog Timer Mode
160/430
COUNT
VALUE
9
WRITE WDTRH,WDTRL
COUNT RELOAD
PRODUCE
WRITE AAh,55h
INTO WDTRL
WD EN=0
G
TIMER START COUNTING
10.1.3.4 Non-Stop Operation
In Watchdog Mode, a Halt instruction is regarded
as illegal. Execution of the Halt instruction stops
further execution by the CPU and interrupt ac-
knowledgment, but does not stop INTCLK, CPU-
CLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regard-
less of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
The Output mode should not be enabled, since in
this context it is meaningless.
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
SOFTWARE FAIL
VA00220
RESET

Related parts for ST92124V1Q-Auto