ST92F150CV1 STMicroelectronics, ST92F150CV1 Datasheet - Page 418

• Manufacturer Part Number: ST92F150CV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150CV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92F124/F150/F250 - KNOWN LIMITATIONS
KNOWN LIMITATIONS (Cont’d)
Workaround 2
Workaround 2 (see
FMP=2 and the CAN cell is receiving, if not the
FIFO can be released immediately. If yes, the pro-
gram goes through a sequence of test instructions
on the RX pin that last longer than the time be-
tween the acknowledge dominant bit and the crit-
ical time slot. If the Rx pin is in recessive state for
more than 8 CAN bit times, it means we are now
Figure 6. Reception with TCAN=12/f
Figure 7. Workaround 2 in Assembler
418/429
1
asm (“
_release:
“);
Sampling of Rx pin
CAN Bus signal
spp #48
ld
and
cp
jxnz
pushw RR232
srp
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
popw
r0, R244
r0, #3
r0, #2
_release
#31
r1.5, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
r12.3, _release
or R244, #32
RR232
Figure
R R R
7) first tests that
/*
/* set CAN0_CTRL page
/* Use spp #36 for CAN1
/* For FIFO 0
/* NB: Replace R244 with R245 for FIFO 1
/*
/*
/* (JRNE instruction)
/* if FMP is not 2 then FIFO
/* release can be done
/* push working group
/* set group F as working group
/* REC bit of CMSR register
/* sample RX bit for 8 bit time
/* ie. 11 btjf instructions
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/* NB: Replace R244 with R245 for FIFO 1
/* restore previous working group
D
CPU
R R R
set RFOM bit of CRFR0 register
and sampling time is 16/f
D
after the acknowledge and the critical slot. If a
dominant bit is read on the bus, we can release the
FIFO immediately. This workaround has to be
written in assembly language to avoid the compiler
optimizing the test sequence.
The implementation shown here is for the CAN
bus maximum speed (1MBd @ 8MHz CPU clock).
R R R
D
CPU
Bytes/cycles
R R R
2/4
2/4
3/6
3/6
2/6
2/8 or 10
2/4
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6 or 10 if jmp
3/6
2/10
D
R R R
D
*/
*/
*/
*/
*/
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