ST92F150CV1 STMicroelectronics, ST92F150CV1 Datasheet - Page 427

• Manufacturer Part Number: ST92F150CV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150CV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

KNOWN LIMITATIONS (Cont’d)
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit fre-
q u e n c y o f 1 9 2 0 0 b a u d ( f C P U = 8 M H z a n d
SCIBRR=0xC9), the wrong break duration occur-
rence is around 1%.
Analysis
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1)x1.4=49 bits. This is
composed of:
- the synch break field (14 bits),
- the synch field (10 bits),
- the identifier field (10 bits).
Every LIN frame starts with a break character.
Adding an idle character increases the length of
each header by 10 bits. When the problem oc-
curs, the header length is increased by 11 bits and
becomes ((14+11)+10+10+1)=45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
ST92F124/F150/F250 - KNOWN LIMITATIONS
between the sync field and the ID smaller than 4
bits, i.e. 208us at 19200 baud.
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be better to keep the break generation se-
quence as it is.
13.8.10 LIN MASTER MODE NOT AVAILABLE
ON SCI-A
LIN Synch Breaks (13 low bits) generation is not
possible on SCI-A. LINE bit has no effect on break
length.
13.8.11 LIMITATIONS ON LQFP64 DEVICES
13.8.11.1
LQFP64 DEVICES
ADC Channels from AIN0 to AIN7 are not present
on LQFP64 devices.
13.8.11.2 EFT0 AND EFT1 NOT AVAILABLE ON
LQFP64 DEVICES
Extended Function Timers are not present on
LQFP64 devices.
AIN[7:0]
NOT
AVAILABLE
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