LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 24

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
Application Information
Functional Overview
The LMH1983 is an analog phase locked loop (PLL) clock
generator that can output simultaneous clocks at any of a va-
riety of video and audio rates, synchronized or “genlocked” to
H sync and V sync input reference timing. The LMH1983 fea-
tures an output Top of Frame (TOF) pulse generator for each
of its four channels, each with programmable timing that can
also be synchronized to the reference frame. The clock gen-
erator uses a two-stage PLL architecture. The first stage is a
VCXO-based PLL (PLL1) that requires an external 27 MHz
VCXO and loop filter. In Genlock mode, PLL1 can phase lock
the VCXO clock to the input reference. The use of a VCXO
provides a low phase noise clock source even when the
LMH1983 is configured with a low loop bandwidth, which is
necessary to attenuate input timing jitter for minimum jitter
transfer. The combination of the external VCXO, external loop
filter, and programmable PLL parameters can provide flexi-
bility for the system designer to optimize the loop bandwidth
and loop response for the application.
Depending on mode, the second stage consists of three PLLs
(PLL2, PLL3, PLL4) with integrated VCOs and loop filters.
These PLLs continually track the reference VCXO clock
phase from PLL1 regardless of the device mode. The PLL2
and PLL3 have pre-configured divider ratios to provide fre-
quency multiplication or translation from the VCXO clock
frequency to generate the two common HD clock rates (148.5
MHz and 148.35 MHz). PLL4 is pre-configured to generate
an audio clock which defaults to a 24.576 MHz output, al-
though PLL4 has several registers which allow it to be re-
configured for a variety of applications.
The VCO PLLs use a high loop bandwidth to assure PLL sta-
bility, so the VCXO must provide a stable low-jitter clock
reference to ensure optimal output jitter performance. Any
unused clock or TOF output can be put in Hi-Z mode, which
can be useful for reducing power dissipation as well as re-
ducing jitter or phase noise on the active clock output. The
TOF pulse can be programmed to indicate the start (top) of
frame and even provide format cross-locking. The output for-
mat registers should be programmed to specify the output
timing (output clocks and TOF pulse), the output timing offset
relative to the reference, and the output initialization (align-
ment) to the reference frame. If unused, the TOF output can
also be put in Hi-Z mode.
When a loss of reference occurs during genlock, PLL1 can
default to either Free-run or Holdover operation. When Free-
run is selected, the output frequency accuracy will be deter-
mined by the external bias on the free-run control voltage
input pin, VC_FREE-RUN. When Holdover is selected, the
loop filter can hold the control voltage to maintain short-term
output phase accuracy for a brief period in order to allow the
application to select the secondary input reference and re-
lock the outputs. These options in combination with proper
PLL1 loop response design can provide flexibility to manage
output clock behavior during loss and re-acquisition of the
24
reference. The reference status and PLL lock status flags can
provide real-time status indication to the application system.
The loss of reference and lock detection thresholds can also
be configured.
I
The protocol of the I
followed by a byte which consists of a seven-bit slave device
address and a Read/Write bit as an LSB. The default address
of the LMH1983 for write sequences is CCh (11001100) and
for read addresses is CDh (11001101). The base address can
be changed with the ADDR pin — with ADDR Open, the base
address is 66h (which when left shifted becomes the CCh
address), with ADDR connected to GND, the base address is
65h, and with ADDR connected to V
67h.
Write Sequence
The write sequence begins with a start condition, which con-
sists of the master pulling SDA low, while SCL is high, next
the slave address is sent, the address is made up of the 7 bit
address, followed by the read/write bit, which for a write is (0).
For the default base address of 66h, (1100110), the 0 is ap-
pended to the end, and the net address is CCh. Each byte
sent after the address is followed by an ACK bit. When SCK
is high, the master will release the SDA line, the slave pulls
SDA low to acknowledge. Once the device address has been
sent, the next byte sent is the register address following the
register address and the ACK, the data byte is sent. When
more than one data byte is sent, the address is automatically
incremented so that the data is written into the next address
location. Note in the Write Sequence Timing diagram that
there is an ACK bit following each data byte.
Read Sequence
Read Sequences are made up of two I
is the address access transfer, which consists of a write se-
quence that transfers only the address to be accessed. The
second is the data read transfer which starts at the address
indicated in the first transfer, and increments to the next ad-
dress, continuing to read addresses until a stop condition is
encountered. The address access transfer is shown in the
timing diagram below, it consists of a start pulse, the slave
device address including the read/write bit (a zero, indicating
a write), and then its ACK bit. The next byte is the address to
be read, followed by the ACK bit, and the stop bit to indicate
the end of the address access transfer. The subsequent read
data transfer shown consists of the start pulse, the slave de-
vice address including the read/write bit (this time a ONE,
indicating that the data is to be read) and the ACK bit. The
next byte is the data read from the initial access address. After
each data byte read, the address is incremented, so contin-
uing to read from the device will provide the data in subse-
quent addresses. Each byte is separated from the previous
byte by an ACK bit, and the end of the read sequence is in-
dicated with a STOP bit.
2
C Interface Protocol
2
C interface begins with the start pulse,
DD
2
, the base address is
C transfers. The first