LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 25

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Initialization
Under some circumstances, it is possible for an LMH1983 to
power up in an anomalous state in which the output of PLL3
exhibits a large amount of cycle to cycle jitter. A simple reg-
ister write after power up will prevent the device from remain-
ing in this state. Writing to register 0x09 with a 0x02, and then
writing to register 0x09 with a 0x00 insures that the device will
not exhibit the poor duty cycle performance on CLKout3
Reference detection
The default mode for the device is to use 'Auto Format Detect'
in which the device determines the reference format from
among those shown in the Auto Format Detection Code table,
and sets up the internal configurations accordingly. There are
31 pre-defined formats, plus one format that the user can de-
fine which will be recognized. The way that the device recog-
nizes a format is by making a measurement of the H
frequency, and looking at the V
if the reference input format is an interlaced or progressive
input. For some formats such as a 10 MHz or 27 MHz refer-
ence, if H
device will not properly recognize the reference input and it
will not lock properly to the reference. Because of this, if H
has one of these 'special' signals on it, V
muted.
Control of PLL1
PLL1 generates a 27 MHz reference that is used as the pri-
mary frequency reference for all of the other PLLs in the
IN
and V
IN
are creating a spurious input, then the
IN
and F
IN
Read Sequence — Address Access Transfer
IN
inputs, to determine
and F
Read Sequence — Data Read Transfer
Write Sequence Timing diagram
IN
should be
IN
input
IN
25
device. PLL1 has a dual loop architecture with the primary
loop locking the external 27 MHz VCXO to a harmonic of the
H
which may be used in genlock operations, this second loop
compares the phase of the TOF1 output signal from the
LMH1983 to the F
primary loop in order to bring the frame alignment of the output
signals into sync with the input reference. How to control this
functionality is described in the section “TOF1 Alignment”
Since PLL2, PLL3 and PLL4 all have PLL1 as their input ref-
erence, the performance of PLL1 affects the performance of
all four clock outputs. The loop filters for the other three PLLs
are all internal, and the bandwidths are set significantly higher
than that of PLL1, so all of the low frequency jitter character-
istics of all four clock outputs are determined by the loop
response of PLL1. Accordingly, special attention should be
paid the PLL1's loop bandwidth and damping factor.
The loop response is primarily determined by the loop filter
components and the loop gain. A passive second order loop
filter consisting of R
sufficient input jitter attenuation for most applications. In some
cases, a higher order filter may be used to further shape the
low frequency response of PLL1.
Several of these parameters are set by the device automati-
cally, for example the charge pump current and the value of
'N'. When the input reference format changes, both N and the
charge pump current are updated, N is changed to allow for
lock to the new reference, and the charge pump current is
adjusted to try to maintain constant loop bandwidth.
The primary locking mechanism for PLL1 is to lock the 27 MHz
output to a multiple of the H
IN
signal. In addition to this loop, there is a secondary loop
IN
signal. This second loop may override the
S
, C
S
and C
IN
frequency, however there is a
P
components can provide
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