TMP86xy08I/S/DMG/NG Toshiba, TMP86xy08I/S/DMG/NG Datasheet - Page 64

• Manufacturer Part Number: TMP86xy08I/S/DMG/NG
• Manufacturer: Toshiba

Specifications of TMP86xy08I/S/DMG/NG

• Package: SSOP30/SDIP30
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 4/8
• Ram Size: 256/256
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: 6
• Adc 10-bit Channels: -
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

6. Time Base Timer (TBT)
6.1 Time Base Timer
Time Base Timer Control Register
6.1.1 Configuration
6.1.2 Control
timer interrupt (INTTBT).
(0036H)
TBTCR
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
TBTEN
TBTCK
Time Base Timer is controlled by Time Base Timer control register (TBTCR).
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
23
21
16
14
13
12
11
(DVOEN)
or fs/2
or fs/2
9
or fs/2
or fs/2
or fs/2
or fs/2
or fs/2
or fs/2
7
Time Base Timer
enable / disable
Time Base Timer interrupt
Frequency select : [Hz]
15
13
8
6
5
4
3
TBTCK
Time base timer control register
6
(DVOCK)
Figure 6-1 Time Base Timer configuration
MPX
3
TBTCR
5
Source clock
(DV7CK)
4
0: Disable
1: Enable
TBTEN
000
001
010
011
100
101
110
111
TBTEN
Falling edge
Page 53
3
detector
DV7CK = 0
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
NORMAL1/2, IDLE1/2 Mode
fc/2
2
23
21
16
14
13
12
11
9
TBTCK
1
DV7CK = 1
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
0
15
13
8
6
5
4
3
(Initial Value: 0000 0000)
release request
INTTBT
interrupt request
IDLE0, SLEEP0
SLEEP1/2
SLOW1/2
TMP86C808DMG
Mode
fs/2
fs/2
–
–
–
–
–
–
15
13
R/W